초록 ▼

A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. This allows one RAM in each group to be accessed with a memory cycle in

A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. This allows one RAM in each group to be accessed with a memory cycle in unison with one RAM in each other group, up to the number of groups. During such a memory cycle each RAM can receive a different address. A tile is the collection of pixel locations associated with a collection of addresses sent to the RAM\s. Because of the regular nature of the permutations these locations may be regions bounded by a single boundary that may be rectangular and of varying size and shape. Changing the mapping of (X, Y) pixel addresses to RAM addresses for the groups changes the size and shape of the tiles. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separated cache. Caching allows the principle of locality to substitute shorter bit-cycles to the cache for memory cycles to the frame buffer, resulting in improved memory throughput. A group rotator and associated group-sized shift register per bit-plane cooperate during refresh to reorder and serialize the pixels of sixteen by one tiles.

대표청구항 ▼

A method of serializing the content of a graphics system frame buffer having a bit-plane per bit of pixel value, for each bit-plane the method comprising the steps of: a. partitioning the frame buffer RAM\s into groups containing equal numbers of RAM\s; b. applying separate addresses to each group;

A method of serializing the content of a graphics system frame buffer having a bit-plane per bit of pixel value, for each bit-plane the method comprising the steps of: a. partitioning the frame buffer RAM\s into groups containing equal numbers of RAM\s; b. applying separate addresses to each group; c. storing n-many bits at each address in each group, n an integer greater than one determining the number of pixel values in each group; d. partitioning the groups into first and second banks of equal numbers of groups; e. simultaneously enabling all groups in the first bank, disabling the groups in the second bank, while applying selected addresses to each group and reading the data from those groups; f. capturing the n-many bits from each group into associated n-bit latches; g. for a selected ordering of the various n-bit latches, parallel loading a shift register with the outputs of each n-bit latch in the selected ordering, one n-bit latch at a time; while subsequently h. shifting the shift register n-many times after each parallel load in step g to produce a serial bit stream representing n pixels; i. simultaneously disabling all groups in the first bank, enabling all groups in the second bank, while applying the same addresses as in step e to all groups and reading the data from those groups; j. repeating steps f, g and h subsequent to step i; and k. combining the serial bit streams from each bit-plane into a sequence of multi-bit pixel values.