이 특허에 인용된 특허 (15) 인용/피인용 타임라인 분석

1. Huberman Bernardo A. (Palo Alto CA) Hogg Tad H. (Anchorage AK), Adaptive self-repairing processor array.

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2. Johnsen Ottar (Middletown NJ), Apparatus and method for compression of facsimile information by pattern matching.

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3. Barnes George H. (Wayne PA) Lundstrom Stephen F. (Wayne PA) Shafer Philip E. (Holmes PA), Array processor architecture connection network.

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4. Morton Steven G. (Oxford CT), Associative array with five arithmetic paths.

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5. Sternberg Stanley R. (Ann Arbor MI) Lougheed Robert M. (Ann Arbor MI), Bit enable circuitry for an image analyzer system.

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6. Rawlings Robert L. (El Toro CA) Watson Morris G. (Mission Viejo CA), Data communications subsystem.

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7. McCanny John V. (Belfast GB5) McWhirter John G. (Malvern GB2) Wood Kenneth W. (Newcastle-upon-Tyne GB2), Digital data processor for multiplying data by a coefficient set.

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8. Kent Ernest W. (Gaithersburg MD), Image processor.

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9. Cooper Leon N. (Providence RI) Elbaum Charles (Providence RI), Information processing system.

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10. Cooper Leon N. (Providence RI) Elbaum Charles (Providence RI), Information processing system using threshold passive modification.

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11. Sternberg Stanley R. (1606 Hillridge Ann Arbor MI 48103) Dargel William O. (90 W. Joy Rd. Ann Arbor MI 48105) Lougheed Robert M. (1206 Wines Dr. Ann Arbor MI 48103) McCubbrey David L. (125 W. Hoover , Neighborhood transformation logic circuitry for an image analyzer system.

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12. McCubbrey David L. (Ann Arbor MI), Parallel pipeline image processor.

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13. Slack Thomas B. (Oxford CT) Denenberg Jeffrey N. (Trumbull CT), Probabilistic learning element.

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14. Kung Hsiang-Tsung (Pittsburgh PA) Leiserson Charles E. (Pittsburgh PA), Systolic array apparatuses for matrix computations.

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15. Ackland, Bryan D.; Burr, David J.; Weste, Neil H. E., Time warp signal recognition processor for matching signal patterns.

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이 특허를 인용한 특허 (179) 인용/피인용 타임라인 분석

1. Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Kuchinski David Christopher ; Knowles Billy Jack ; Nier Richard Edward ; Retter Eric Eugene ; Richardson Robert Reist ; Rolfe, APAP I/O programmable router.

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2. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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3. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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4. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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5. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.

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11. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Grice Donald George ; Kogge Peter Michael ; Kuchinski David Christopher ; Knowles Billy Jack ; Lesmeis, Advanced parallel array processor (APAP).

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12. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Grice Donald George ; Kogge Peter Michael ; Kuchinski David Christopher ; Knowles Billy Jack ; Lesmeis, Advanced parallel array processor (APAP).

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13. Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Grice Donald G. (Kingston NY) Knowles Billy J. (Kingston NY) Lesmeister , Advanced parallel array processor I/O connection.

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14. Dapp Michael C. (Endwell NY) Barker Thomas N. (Vestal NY) Dieffenderfer James W. (Owego NY) Knowles Billy J. (Kingston NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Rolfe David , Advanced parallel processor including advanced support hardware.

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15. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.

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16. Hennenhoefer Eric Todd ; Raymond Jonathan Henry, Apparatus and method for partitioning multiport rams.

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17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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18. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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19. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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20. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.

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21. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.

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22. Wilkinson Paul A. (Apalachin NY) Kogge Peter M. (Endicott NY), Array processor dotted communication network based on H-DOTs.

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23. Dieffenderfer James Warren ; Kogge Peter Michael ; Wilkinson Paul Amba ; Schoonover Nicholas Jerome, Associative parallel processing system.

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24. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Autonomous SIMD/MIMD processor memory elements.

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25. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.

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26. Vorbach, Martin, Chip including memory element storing higher level memory data on a page by page basis.

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27. Kan,Makiko, Circuit design method, apparatus, and program.

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28. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.

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29. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.

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30. Lee Tsung-En Andy ; Cox Donald C., Computation using codes for controlling configurable computational circuit.

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31. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.

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32. Vorbach, Martin; Nuckel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.

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33. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.

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34. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.

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35. Wilkinson Paul Amba ; Barker Thomas Norman ; Dieffenderfer James Warren ; Kogge Peter Michael ; Lesmeister Donald Michael ; Richardson Robert Reist ; Smoral Vincent John, Controller for a SIMD/MIMD array having an instruction sequencer utilizing a canned routine library.

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36. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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37. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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38. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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39. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.

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40. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.

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41. Vorbach, Martin, Data processing system.

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42. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.

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43. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.

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44. Marks, Maury I., Direction finding method and system using digital directional correlators.

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45. Vorbach Martin Andreas,DEX ; Munch Robert Markus,DEX, Dynamically reconfigurable data processing system.

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46. Marketkar, Nandu J.; Benham, John R.; Knight, Jr., Thomas F.; Amirtharajah, Rajeevan, Electromagnetic coupler circuit board having at least one angled conductive trace.

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47. Marketkar,Nandu J.; Knight, Jr.,Thomas F.; Benham,John R.; Amirtharajah,Rajeevan, Electromagnetic coupler flexible circuit with a curved coupling portion.

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48. Furtek, Frederick Curtis; Master, Paul L., External memory controller.

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49. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.

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50. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.

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51. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.

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52. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Lesmeister Donald Michael ; Miles Richard Ernest ; Nier Richard Edward ; Richards, Fully distributed processing memory element.

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53. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.

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54. Scheuermann,Walter James, Hardware implementation of the secure hash standard.

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55. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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56. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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57. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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58. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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59. Martin Vorbach DE; Robert Munch DE, I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures.

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60. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.

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61. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.

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62. Vorbach,Martin; M��nch,Robert, I/O and memory bus system for DFPS and units with two-or multi-dimensional programmable cell architectures.

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63. Vorbach Martin,DEX ; Munch Robert,DEX, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.

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64. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.

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65. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.

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66. Vorbach,Martin; M？nch,Robert, I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures.

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67. Ikeda, Kenji; Shimura, Hiroshi; Sato, Tomoyoshi, IC containing matrices of plural type operation units with configurable routing wiring group and plural delay operation units bridging two wiring groups.

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68. Jones Simon David,GBX, Image processing system.

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69. Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.

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70. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.

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71. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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72. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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73. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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74. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.

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75. Ryu, Soo jung; Kim, Jeong wook; Kim, Suk jin; Kim, Hong Seok; Kong, Jun jin, Loop accelerator and data processing system having the same.

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76. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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77. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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78. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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79. Juan, Yujen, Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration.

    상세보기
80. Baraniuk, Richard; Baron, Dror Z.; Duarte, Marco F.; Elnozahi, Mohamed; Wakin, Michael B.; Davenport, Mark A.; Laska, Jason N.; Tropp, Joel A.; Massoud, Yehia; Kirolos, Sami; Ragheb, Tamer, Method and apparatus for on-line compressed sensing.

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81. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for position independent reconfiguration in a network of multiple context processing elements.

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82. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for retiming in a network of multiple context processing elements.

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83. Mirsky, Ethan; French, Robert; Eslick, Ian, Method and apparatus for retiming in a network of multiple context processing elements.

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84. Mirsky,Ethan; French,Robert; Eslick,Ian, Method and apparatus for retiming in a network of multiple context processing elements.

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85. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.

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86. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.

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87. Master, Paul L., Method and system for achieving individualized protected space in an operating system.

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88. Master, Paul L., Method and system for creating and programming an adaptive computing engine.

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89. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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90. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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91. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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92. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

    상세보기
93. Scheuermann, W. James, Method and system for reconfigurable channel coding.

    상세보기
94. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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95. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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96. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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97. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).

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98. Vorbach, Martin, Method for debugging reconfigurable architectures.

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99. Vorbach, Martin, Method for debugging reconfigurable architectures.

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100. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.

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101. Vorbach,Martin, Method for debugging reconfigurable architectures.

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102. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.

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103. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.

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104. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.

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105. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.

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106. Vorbach Martin,DEX ; Munch Robert,DEX, Method for the automatic address generation of modules within clusters comprised of a plurality of these modules.

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107. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.

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108. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.

     상세보기
109. Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).

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110. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).

     상세보기
111. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.

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112. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.

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113. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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114. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

     상세보기
115. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

     상세보기
116. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

     상세보기
117. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.

     상세보기
118. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.

     상세보기
119. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable unit.

     상세보기
120. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.

     상세보기
121. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.

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122. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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123. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

     상세보기
124. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

     상세보기
125. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.

     상세보기
126. Vorbach, Martin, Methods and devices for treating and/or processing data.

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127. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Methods and systems for transferring data between a processing device and external devices.

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128. Vorbach, Martin; Baumgarte, Volker, Multiprocessor having runtime adjustable clock and clock dependent power supply.

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129. Wise, Adrian P.; Boyd, Kevin; Claydon, Anothy Peter; Robbins, William P.; Finch, Helen R.; Sotheran, Martin W.; Jones, Anthony Mark, Multistandard video decoder and decompression system for processing encoded bit streams including a standard-independent stage and methods relating thereto.

     상세보기
130. Wise, Adrian P; Sotheran, Martin W; Robbins, William P; Jones, Anthony M; Finch, Helen R; Boyd, Kevin J; Claydon, Anthony Peter J, Multistandard video decoder and decompression system for processing encoded bit streams including start code detection and methods relating thereto.

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131. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Rolfe David Bruce, N-dimensional modified hypercube.

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132. Knowles Billy J. (Kingston NY) Collins Clive A. (Poughkeepsie NY) Desnoyers Christine M. (Pine Bush NY) Grice Donald G. (Kingston NY) Rolfe David B. (West Hurley NY), Parallel computer system providing multi-ported intelligent memory.

     상세보기
133. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Parallel processing system having asynchronous SIMD processing and data parallel coding.

     상세보기
134. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.

     상세보기
135. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Partitioning of processing elements in a SIMD/MIMD array processor.

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136. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.

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137. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.

     상세보기
138. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.

     상세보기
139. Vorbach Martin,DEX ; Munch Robert,DEX, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like).

     상세보기
140. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).

     상세보기
141. Martin Vorbach DE; Robert Munch DE, Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like).

     상세보기
142. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.

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143. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.

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144. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.

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145. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.

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146. Robinson Jeffrey I. ; Rouse Keith, Programmable digital signal processor integrated circuit device and method for designing custom circuits from same.

     상세보기
147. Bolstad Gregory D. (Orange CA) Neeld Kenneth B. (Fountain Valley CA) Robie Charles J. (Fullerton CA) Staub John R. (Corona CA), Programmable systolic array system arranged in a found arrangement for passing data through programmable number of cells.

     상세보기
148. Vorbach, Martin, Reconfigurable elements.

     상세보기
149. Vorbach, Martin, Reconfigurable elements.

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150. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.

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151. Vorbach,Martin; M？nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.

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152. Vorbach, Martin, Reconfigurable sequencer structure.

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153. Vorbach, Martin, Reconfigurable sequencer structure.

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154. Vorbach, Martin, Reconfigurable sequencer structure.

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155. Vorbach, Martin, Reconfigurable sequencer structure.

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156. Vorbach,Martin, Reconfigurable sequencer structure.

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157. Vorbach, Martin; Bretz, Daniel, Router.

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158. Vorbach,Martin; Bretz,Daniel, Router.

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159. Vorbach Martin,DEX ; Munch Robert,DEX, Run-time reconfiguration method for programmable units.

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160. Vorbach,Martin; M？nch,Robert, Run-time reconfiguration method for programmable units.

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161. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.

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162. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.

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163. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, SIMD/MIMD array processor with vector processing.

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164. Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Retter E, SIMD/MIMD processing memory element (PME).

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165. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, SIMD/MIMD processing synchronization.

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166. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael, SIMIMD array processing system.

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167. Branco Richard G. (Westmont NJ) Monastra Edward J. (Voorhees NJ) Ovadia David J. (New York NY), Serial-parallel digital signal processor.

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168. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Slide bus communication functions for SIMD/MIMD array processor.

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169. Wilkinson Paul Amba ; Barker Thomas Norman ; Dieffenderfer James Warren ; Kogge Peter Michael, Slide network for an array processor.

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170. Master,Paul L.; Watson,John, Storage and delivery of device features.

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171. Eslick, Ian S.; Williams, Mark; French, Robert S., System and method for executing hybridized code on a dynamically configurable hardware environment.

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172. Eslick,Ian S.; Williams,Mark; French,Robert S., System and method for executing hybridized code on a dynamically configurable hardware environment.

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173. Songer,Christopher; Eslick,Ian S.; French,Robert S., System and method for preparing software for execution in a dynamically configurable hardware environment.

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174. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.

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175. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.

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176. Lu, Haw-minn; Huang, Alan, Systems and methods for overlaid switching networks.

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177. Means Robert W. (Rancho Santa Fe CA) Sklar Horace J. (Escondido CA), Systolic array image processing system and method.

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178. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.

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179. Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.

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