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Process for defining vias through silicon nitride and polyimide 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/308
출원번호 US-0205009 (1988-05-31)
발명자 / 주소
  • Nanda Madan M. (Reston VA) Peterman Steven L. (Manassas VA) Stanasolovich David (Manassas VA)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 35  인용 특허 : 12

초록

A process for defining vias through a polyimide and silicon nitride layer is disclosed. After the deposition of a first layer of silicon nitride and a second layer of polyimide, a layer of photoresist capable of producing negatively sloped walls is then lithographically defined with a pattern of via

대표청구항

In an integrated circuit chip having a plurality of semiconductor devices, a process for defining self-aligned vias through a silicon nitride layer and a polyimide layer comprising the following steps in the following order: depositing a layer of silicon nitride over said semiconductor devices, said

이 특허에 인용된 특허 (12)

  1. Matthews James A. (Santa Clara CA), CMOS Process with unique plasma etching step.
  2. Takada, Tadakazu, Etching method for semiconductor devices.
  3. Sebesta Edward H. (San Francisco CA), Lift-off process for depositing metal on a substrate.
  4. Farrar Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Kroll Charles T. (Raleigh NC), Method for forming dense multilevel interconnection metallurgy for semiconductor devices.
  5. Bukhman Yefim (Tempe AZ), Method for forming semiconductor devices.
  6. Gleason Robert T. (Burlington VT) Linde Harold G. (Richmond VT), Method of forming an RIE etch barrier by in situ conversion of a silicon containing alkyl polyamide/polyimide.
  7. Logan Joseph S. (Poughkeepsie NY) Mauer ; IV John L. (Sherman CT) Rothman Laura B. (Sherman CT) Schwartz Geraldine C. (Poughkeepsie NY) Standley Charles L. (Wappingers Falls NY), Planar multi-level metal process with built-in etch stop.
  8. Wolf Stanley (Sunset Beach CA) Atwood Warren C. (Los Angeles CA), Polyimide inter-metal dielectric process.
  9. Aoyama Masaharu (Fujisawa JPX) Abe Masahiro (Yokohama JPX) Ajima Takashi (Kamakura JPX) Yonezawa Toshio (Kitakyushu JPX), Semiconductor device having a multilayer wiring structure using a polyimide resin.
  10. Almgren Carl W. (Austin TX), Slope etch of polyimide.
  11. Cronin John E. (Milton VT) Kaanta Carter W. (Colchester VT), Stud formation method optimizing insulator gap-fill and metal hole-fill.
  12. Anderson ; Jr. Herbert R. (Patterson NY) Sachdev Harbans S. (Wappingers Falls NY) Sachdev Krishna G. (Wappingers Falls NY), Use of depolymerizable polymers in the fabrication of lift-off structure for multilevel metal processes.

이 특허를 인용한 특허 (35)

  1. Belgacem Haba ; Konstantine Karavakis, Components with releasable leads.
  2. Haba, Belgacem; Karavakis, Konstantine, Components with releasable leads.
  3. Kasuga Takashi,JPX ; Tomo Yoichi,JPX, Contact hole forming method.
  4. Harvey Ian Robert ; Gabriel Calvin Todd ; Bothra Subhas, In-situ corner rounding during oxide etch for improved plug fill.
  5. Jun Young Kwon,KRX, Insulating layer structure for semiconductor device.
  6. Park Jong-Sung,KRX, Method for fabricating semiconductor device with an increased process tolerance.
  7. Joseph, John R.; Luo, Wenlin; Lear, Kevin L.; Bryan, Robert P., Method of improving the fabrication of etched semiconductor devices.
  8. Haba, Belgacem; Karavakis, Konstantine, Method of making components with releasable leads.
  9. Haba, Belgacem; Karavakis, Konstantine, Method of making components with releasable leads.
  10. Haba,Belgacem; Karavakis,Konstantine, Method of making components with releasable leads.
  11. Kaneko Satoru,JPX ; Ohkoda Toshiyuki,JPX, Method of manufacturing a semiconductor integrated circuit device.
  12. Eppler, Aaron; Srinivasan, Mukund; Chebi, Robert, Process for etching dielectric films with improved resist and/or etch profile characteristics.
  13. Thackeray, James W.; Mori, James Michael; Teng, Gary Ganghui, Thick film photoresists and methods for use thereof.
  14. Morita,Sumihito; Oki,Naruaki; Watanabe,Toshinori; Shinozaki,Hiroko, Thin film magnetic head having partial insulating layer formed on bottom pole layer through gap layer and method of manufacturing the same.
  15. Herrin, Russell T.; Lindgren, Peter J.; Sprogis, Edmund J.; Stamper, Anthony K., Through silicon via lithographic alignment and registration.
  16. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  17. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  18. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  19. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  20. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  21. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  23. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  24. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  25. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  26. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  27. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  28. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  29. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  30. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  31. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  32. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  33. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  34. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  35. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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