$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Process for making integrated-circuit device metallization 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/283
출원번호 US-0282808 (1988-12-09)
발명자 / 주소
  • Rana Virendra V. S. (South Whitehall Township
  • Lehigh County PA) Tsai Nun-Sian (South Whitehall Township
  • Lehigh County PA)
출원인 / 주소
  • AT&T Bell Laboratories (Murray Hill NJ 02)
인용정보 피인용 횟수 : 12  인용 특허 : 12

초록

In the manufacture of an integrated-circuit device, periodic interruption of grain growth during chemical vapor deposition of a metal film results in enhanced surface smoothness and ease of patterning. Interruption of grain growth is by deposition of an auxiliary material which, in the interest of h

대표청구항

A method for making an integrated-circuit device which includes a dielectric, comprising forming a metallization on said dielectric, and forming said metallization comprising the steps of: depositing a first metal layer, forming on said first metal layer a grain-growth interrupting layer which is se

이 특허에 인용된 특허 (12)

  1. Ueda Yoshiya (Yokohama JPX) Okutsu Fumie (Kawasaki JPX) Momotomi Masaki (Yokohama JPX), Enhanced silicide adhesion to semiconductor and insulator surfaces.
  2. Harada Hiroshi (Itami JPX) Hirata Yoshihiro (Itami JPX) Tosa Masanobu (Itami JPX), Homogeneous fine grained metal film on substrate and manufacturing method thereof.
  3. Cheung Robin W. (Cupertino CA) Ho Bernard W. K. (Fremont CA) Chen Hsiang-Wen (Cupertino CA) Chan Hugo W. K. (Fremont CA), Low resistance metal contact for silicon devices.
  4. Joshi Rajiv V. (Yorktown Heights NY), Low stress tungsten films by silicon reduction of WF6.
  5. Rogers Steven H. (Midwest City OK) Hwang Thomas J. (Fremont CA), Method for forming improved contacts between interconnect layers of an integrated circuit.
  6. Wilson Ronald H. (Schenectady NY), Method for nucleating and growing tungsten films.
  7. Hooper Robert C. (Houston TX) Roane Bobby A. (Manvel TX) Verret Douglas P. (Sugar Land TX), Method of making metal contacts and interconnections for VLSI devices with copper as a primary conductor.
  8. Kim Manjin J. (Schenectady NY) Brown Dale M. (Schenectady NY) Cohen Simon S. (Schenectady NY) Gorowitz Bernard (Clifton Park NY) Saia Richard J. (Scotia NY), Method of making mo/tiw or w/tiw ohmic contacts to silicon.
  9. Raby Joseph S. (W. Melbourne FL), Process using tungsten for multilevel metallization.
  10. Flanner Janet M. (Union City CA) van der Putte Paulus Z. A. (Eindhoven NLX), Self-aligned metallization for semiconductor device and process using selectively deposited tungsten.
  11. Okumura Katsuya (Yokohama JPX), Semiconductor device with a diffusion barrier contact of a refractory metal nitride and either carbon or boron.
  12. Lee Keunmyung (Redwood City CA) Nishi Yoshio (Palo Alto CA), Via connection with thin resistivity layer.

이 특허를 인용한 특허 (12)

  1. Itoh Toshio ; Chang Mei, CVD process for DCS-based tungsten silicide.
  2. Anna Lee Y. Tonkovich ; Yong Wang ; Yufei Gao, Catalyst, method of making, and reactions using the catalyst.
  3. Tonkovich, Anna Lee Y.; Wang, Yong; Gao, Yufei, Catalyst, method of making, and reactions using the catalyst.
  4. Ngo, Minh Van; Tran, Minh Q., Laser thermal annealing for Cu seedlayer enhancement.
  5. Anna Lee Y. Tonkovich ; Yong Wang ; Yufei Gao, Long life hydrocarbon conversion catalyst and method of making.
  6. Ghanayem Steve ; Mahajani Maitreyee, Method for forming a gap filling refractory metal layer having reduced stress.
  7. Nakajima,Takashi; Miura,Hideo; Ohta,Hiroyuki; Okamoto,Noriaki, Method of manufacturing semiconductor device having conductive thin films.
  8. Nakajima,Takashi; Miura,Hideo; Ohta,Hiroyuki; Okamoto,Noriaki, Method of manufacturing semiconductor device having conductive thin films.
  9. Nakajima Takashi,JPX ; Miura Hideo,JPX ; Ohta Hiroyuki,JPX ; Okamoto Noriaki,JPX, Semiconductor apparatus having conductive thin films.
  10. Takashi Nakajima JP; Hideo Miura JP; Hiroyuki Ohta JP; Noriaki Okamoto JP, Semiconductor apparatus having conductive thin films.
  11. Nakajima Takashi,JPX ; Miura Hideo,JPX ; Ohta Hiroyuki,JPX ; Okamoto Noriaki,JPX, Semiconductor apparatus having conductive thin films and manufacturing apparatus therefor.
  12. Takashi Nakajima JP; Hideo Miura JP; Hiroyuki Ohta JP; Noriaki Okamoto JP, Semiconductor apparatus having conductive thin films and manufacturing apparatus therefor.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로