초록 ▼

A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconn

A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and host wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment and the passivation covering of the assembly are disclosed.

대표청구항 ▼

A wafer scale integration multiple die integrated circuit structure comprising the combination of: a semiconductor wafer host member having top and bottom planar surfaces; a plurality of receptacle wells each having lateral and bottom surfaces received in selected top surface locations of said wafer

A wafer scale integration multiple die integrated circuit structure comprising the combination of: a semiconductor wafer host member having top and bottom planar surfaces; a plurality of receptacle wells each having lateral and bottom surfaces received in selected top surface locations of said wafer; a plurality of integrated circuit die, each die including a planar top surface having a plurality of electrical connection bonding pads adjacent thereto, a bottom surface, and lateral surfaces joining said top and bottom surfaces, said die being uprightly received one in each of said wafer member receptacle wells with said die top surface and said wafer surface being disposed in substantial planar alignment by the die bottom surface to receptacle well bottom surface thickness of interstitial cured epoxy adhesive means; cured epoxy adhesive means, including a predetermined thermal coefficient of expansion selective particulate filler material uniformly dispersed therein, received in each of said receptacle wells intermediate each respective of said well and die bottom surfaces and said well and die lateral surfaces for physically connecting said die and wafer elements, said adhesive means also including an annularly disposed and planar surface aligned top surface portion bridging between the planar surfaces of said die and wafer.