초록 ▼

A method for fabricating thin-film multilayer interconnect signal planes for connecting semiconductor integrated circuits (chips) is described. In this method, a first pattern of thin-film metallic interconnect lines is formed on a surface of a substrate. Then a first dielectric layer is formed over

A method for fabricating thin-film multilayer interconnect signal planes for connecting semiconductor integrated circuits (chips) is described. In this method, a first pattern of thin-film metallic interconnect lines is formed on a surface of a substrate. Then a first dielectric layer is formed over the entire surface of the substrate covering the pattern of thin-film metallic interconnect lines. A portion of the dielectric layer is then removed to expose the thin-film metallic interconnect lines so that a series of trenches is formed above each interconnect line. The interconnect lines are then electroplated to form a series of thicker metal interconnect lines such that the thicker metal interconnect lines and the dielectric layer form a substantially planar surface. This process can then be repeated in its entirely to form a plurality of interconnect signal planes. In the preferred embodiment, metallic vias are provided between each layer of metallic interconnect lines for electrical connection purposes.

대표청구항 ▼

A device for connecting semiconductor integrated circuit chips, each chip including integrated circuit formed on a chip substrate, said device comprising: a mounting substrate having a fist substantially planar surface; and an interconnect signal plane formed on top of said first substantially plana

A device for connecting semiconductor integrated circuit chips, each chip including integrated circuit formed on a chip substrate, said device comprising: a mounting substrate having a fist substantially planar surface; and an interconnect signal plane formed on top of said first substantially planar surface of said mounting substrate and including a substantially planar pattern of metallic interconnect lines, each lien being in the range of 1 to 10 microns thick and 5 to 20 microns wide, and a dielectric material separating said interconnect lines, said dielectric material and said pattern of metallic interconnect lines forming a second substantially planar surface in spaced relation above said first substantially planar surface, wherein said substantially planar pattern of metallic interconnect lines is an integral portion of said second substantially planar surface, said chips being connected to said interconnect lines of said pattern.