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Process for forming a self-aligned contact structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0566185 (1990-08-13)
발명자 / 주소
  • Woo Michael P. (Austin TX) Mele Thomas C. (Austin TX) Ray Wayne J. (Austin TX) Paulson Wayne M. (Austin TX)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 70  인용 특허 : 5

초록

A self-aligned contact is formed in a multi-layer semiconductor device. In one form, conductive members are formed overlying a substrate material and a first insulating layer is deposited overlying the substrate material and the conductive members. A film of material is deposited on the first insula

대표청구항

A process for fabricating a self-aligned contact in a multi-layer semiconductor device, comprising the steps of: providing a first insulating layer overlying a substrate material; depositing a film of material overlying the first insulating layer and having the ability to be selectively etched to th

이 특허에 인용된 특허 (5)

  1. Riley Paul E. (Columbia MD) Kulkarni Vivek D. (Sunnyvalle CA) Castel Egil D. (Cupertino CA), Etch back detection.
  2. Chan Tsiu C. (Carrollton TX) Han Yu-Pin (Dallas TX), Method for forming a self-aligned source/drain contact for an MOS transistor.
  3. Bridges Jeffrey M. (Dallas TX), Method for forming contacts through a thick oxide layer on a semiconductive device.
  4. Erb Darrell M. (Los Altos CA), Method for making improved contact for integrated circuit structure.
  5. Gray Peter V. (Scotia NY) Baliga Bantval J. (Schenectady NY) Chang Mike F. S. (Cary NC) Pifer George C. (North Syracuse NY), Method of fabricating self aligned semiconductor devices.

이 특허를 인용한 특허 (70)

  1. Jacobsen, Stephen C.; Smith, Fraser M.; Olivier, Marc X., Amphibious robotic crawler.
  2. Zamanian Mehdi, Barrier and landing pad structure in an integrated circuit.
  3. Jacobsen, Stephen C.; Maclean, Brian J.; Pensel, Ralph W.; Hirschi, Christopher R., Conformable track assembly for a robotic crawler.
  4. Chan, Tsiu C.; Huang, Kuei-Wu, Contact in an integrated circuit.
  5. Smith, Fraser M., Coordinated robotic control.
  6. Stamper, Anthony K., Damascene capacitor having a recessed plate.
  7. Stamper, Anthony K., Damascene capacitor having a recessed plate.
  8. Cleeves James M., Disposable post processing for semiconductor device fabrication.
  9. Yaung Dun-Nian,TWX ; Wuu Shou-Gwo,TWX ; Chao Li-Chih,TWX ; Huang Kuo Ching,TWX, Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits.
  10. Nguyen Loi N. ; Bryant Frank R. ; Balasinski Artur P., Dual landing pad structure in an integrated circuit.
  11. Chan Tsiu C. ; Bryant Frank R. ; Nguyen Loi N. ; Balasinski Artur P., Dual landing pad structure including dielectric pocket.
  12. Chen Wenn-Jei (Sunnyvale CA) Tseng Huang-Chung (Santa Clara CA), Edgeless, self-aligned, differential oxidation enhanced and difusion-controlled minimum-geometry antifuse and method of.
  13. Tao, Wei, Etch stop layer for use in a self-aligned contact etch.
  14. Rolfson J. Brett, Integrated circuit and method for forming and integrated circuit.
  15. Nguyen Loi N., Integrated circuit contact structure having gate electrode protection for self-aligned contacts with zero enclosure.
  16. Rolfson J. Brett, Integrated circuit, and method for forming an integrated circuit.
  17. Sandhu Gurtej S. ; Iyer Ravi, Integrated circuitry.
  18. Sandhu Gurtej S. ; Iyer Ravi, Integrated circuitry comprising electrically insulative material over interconnect line tops, sidewalls and bottoms.
  19. Rolfson J. Brett, Interlocking conductive plug for use with an integrated circuit.
  20. Menon,Santosh S.; Bhatt,Hemanshu D.; Pritchard,David, Local interconnect manufacturing process.
  21. Jacobsen, Stephen C.; Olivier, Marc X.; Pensel, Ralph W.; Smith, Fraser M., Method and system for deploying a surveillance network.
  22. Mikagi Kaoru (Tokyo JPX), Method for fabricating semiconductor device with interconnections buried in trenches.
  23. McAnally Peter S. ; McKee Jeffrey A., Method for forming a contact to a substrate.
  24. Mele Thomas C. (Austin TX) Paulson Wayne M. (Austin TX) Baker Frank K. (Austin TX) Woo Michael P. (Austin TX), Method for forming a multi-layer semiconductor device using selective planarization.
  25. Miyai Yoichi,JPX, Method for forming a self-aligned contact.
  26. Chen,Meng Hung; Lin,Shian Jyh; Yu,Chia Sheng, Method for forming self-aligned contact in semiconductor device.
  27. Kuroki,Keiji, Method for manufacturing semiconductor memory.
  28. Zamanian Mehdi (Carrollton TX), Method of forming a barrier and landing pad structure in an integrated circuit.
  29. Chan Tsiu C. ; Huang Kuei-Wu, Method of forming a contact in an integrated circuit.
  30. Kim Myung Seon,KRX ; Back Sun Haeng,KRX, Method of forming a floating gate in a flash memory device.
  31. Chan Tsiu C. (Carrollton TX) Bryant Frank R. (Denton TX) Nguyen Loi N. (Carrollton TX), Method of forming a landing pad structure in an integrated circuit.
  32. Chan Tsiu C. ; Bryant Frank R. ; Nguyen Loi N., Method of forming a landing pad structure in an integrated circuit.
  33. Chan Tsiu C. ; Bryant Frank R. ; Nguyen Loi N., Method of forming a landing pad structure in an integrated circuit.
  34. Miller Robert Otis ; Smith Gregory Clifford, Method of forming a landing pad structure in an integrated circuit.
  35. Nguyen Loi N. ; Bryant Frank R. ; Balasinski Artur P., Method of forming a landing pad structure in an integrated circuit.
  36. Miller Robert Otis ; Smith Gregory Clifford, Method of forming a landing pad sturcture in an integrated circuit.
  37. Nguyen Loi N. ; Bryant Frank R., Method of forming a metal contact to landing pad structure in an integrated circuit.
  38. Nguyen Loi N. ; Bryant Frank R., Method of forming a metal contact to landing pad structure in an integrated circuit.
  39. Jae-Goo Lee KR; Chang-Hyun Cho KR; Gwan-Hyeob Koh KR, Method of forming a self-aligned contact pad for a semiconductor device.
  40. Loi N. Nguyen, Method of forming an integrated circuit contact structure having gate electrode protection for self-aligned contacts with zero enclosure.
  41. Ohsaki Akihiko (Hyogo JPX), Method of forming multi-layer interconnection.
  42. Mitsuhashi Toshiro,JPX, Method of manufacturing a semiconductor device including a process of forming a contact hole.
  43. Chan, Bor-Wen, Method of planarizing polysillicon plug.
  44. Gil-heyun Choi KR; Eung-joon Lee KR; Byeong-jun Kim KR, Methods of forming filled interconnections in microelectronic devices.
  45. Chen Wenn-Jei (Sunnyvale CA), Process of making ESD protection devices for use with antifuses.
  46. Lee Kuo-Hua ; Yu Chen-Hua Douglas, Self-aligned contact window.
  47. Lu Chih-Yuan,TWX, Self-aligned method for forming a narrow via.
  48. Mariko Habu JP; Kazumasa Sunouchi JP; Masami Aoki JP; Tahru Ozaki JP, Semiconductor apparatus formed by SAC (self-aligned contact).
  49. Habu Mariko,JPX ; Sunouchi Kazumasa,JPX ; Aoki Masami,JPX ; Ozaki Tohru,JPX, Semiconductor apparatus formed by SAC (self-aligned contact) method and manufacturing method therefor.
  50. Eimori Takahisa,JPX ; Kimura Hiroshi,JPX, Semiconductor device and manufacturing process thereof.
  51. Eimori, Takahisa; Kimura, Hiroshi, Semiconductor device and manufacturing process thereof.
  52. Nakamura Shunji,JPX, Semiconductor device and method for fabricating the same.
  53. Nakamura, Shunji, Semiconductor device and method for fabricating the same.
  54. Nakamura, Shunji, Semiconductor device and method for fabricating the same.
  55. Inoue, Hiroyuki, Semiconductor device and method for manufacturing the same.
  56. Irie Seishi,JPX ; Sato Takahiro,JPX, Semiconductor device and method of the same.
  57. Kondo Toshihiko (Suwa JPX) Tanaka Kazuo (Suwa JPX) Yasuda Hirofumi (Suwa JPX), Semiconductor device having an inter-layer insulating film disposed between two wiring layers.
  58. Sandhu Gurtej S. ; Iyer Ravi, Semiconductor processing method of forming electrically conductive interconnect lines and integrated circuitry.
  59. Gurtej S. Sandhu ; Ravi Iyer, Semiconductor processing method of forming insulative material over conductive lines.
  60. Jacobsen, Stephen C., Serpentine robotic crawler.
  61. Pensel, Ralph W., Serpentine robotic crawler.
  62. Smith, Fraser M., Serpentine robotic crawler.
  63. Smith, Fraser M.; Olivier, Marc; McCullough, John, Serpentine robotic crawler for performing dexterous operations.
  64. Robins, Scott; Horch, Andrew; Nemati, Farid; Cho, Hyun-Jin, Thyristor-based device including trench dielectric isolation for thyristor-body regions.
  65. Robins, Scott; Horch, Andrew; Nemati, Farid; Cho, Hyun-Jin, Thyristor-based device including trench isolation.
  66. Cho, Hyun-Jin; Horch, Andrew; Robins, Scott; Nemati, Farid, Thyristor-based device over substrate surface.
  67. Cho, Hyun-Jin; Horch, Andrew; Robins, Scott; Nemati, Farid, Thyristor-based device over substrate surface.
  68. Jacobsen, Stephen C.; Marceau, David P., Two-dimensional layout for use in a complex structure.
  69. Liaw Jhon-Jhy,TWX, Use of a wet etch dip step used as part of a self-aligned contact opening procedure.
  70. Horch,Andrew E., Vertical thyristor-based memory with trench isolation and its method of fabrication.
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