초록 ▼

An improved packaged semiconductor device is provided having an electronic component, such as an integrated circuit, enclosed within a single layer ceramic PGA package. A cap, of substantially the same areal dimension as the base, is sealed to the base forming a cavity in which the integrated circui

An improved packaged semiconductor device is provided having an electronic component, such as an integrated circuit, enclosed within a single layer ceramic PGA package. A cap, of substantially the same areal dimension as the base, is sealed to the base forming a cavity in which the integrated circuit is mounted. Input/output pins are attached to through-holes in the base and extend through the base and are exposed by holes in the cap aligned to the through-holes in the base. Extensive glass sealing of the cap to the base, made possible by the substantially co-extensive nature of the cap with respect to the base, provides a sturdy highly reliable seal making the packaged semiconductor device better able to withstand mechanical stress.

대표청구항 ▼

A packaged semiconductor device comprising: a single-layer ceramic base having a first plurality of through-holes therein; an integrated circuit disposed at a predetermined location on said base; terminal means attached to said base extending through said first plurality of through-holes in said bas

A packaged semiconductor device comprising: a single-layer ceramic base having a first plurality of through-holes therein; an integrated circuit disposed at a predetermined location on said base; terminal means attached to said base extending through said first plurality of through-holes in said base and having distal ends extending therefrom, said terminal means providing external electrical connection to said semiconductor device; a cap substantially co-extensive with said base having a second plurality of through-holes therein corresponding with and aligned to said first plurality of through-holes in said base, said cap bonded to said base forming a cavity between said base and said cap hermetically enclosing said integrated circuit within said cavity; and coupling means for electrically coupling said terminal means to said integrated circuit.