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[미국특허] Method of making multilayer printed circuit board 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-003/36
출원번호 US-0374118 (1989-06-30)
발명자 / 주소
  • Sisler John R. (Scott\s Valley CA)
출원인 / 주소
  • Unisys Corp. (Detroit MI 02)
인용정보 피인용 횟수 : 99  인용 특허 : 6

초록 ▼

A method of making a multilayer printed circuit board providing sufficient internal distributed capacitance so as to eliminate the need for the by-pass capacitor conventionally provided in the vicinity of each integrated circuit mounted to the board. The method includes providing one or more fully-c

대표청구항 ▼

A method of making a multilayer printed circuit board comprised of interleaved contiguous conductive and insulative dielectric layers, said method comprising: providing a power-ground plane sandwich component comprised of a curable dielectric layer contiguously sandwiched between a conductive power

이 특허에 인용된 특허 (6) 인용/피인용 타임라인 분석

  1. Hoffarth Joseph G. (Binghamton NY) Wiley John P. (Vestal NY), High performance circuit boards.
    상세보기
  2. Schachter Herbert I. (86 Campbell St. New Hyde Park ; Long Island NY 11040), Method of making a multi-level circuit board.
    상세보기
  3. Ohnuki Hidebumi (Tokyo JPX) Asano Toshiaki (Tokyo JPX) Atarashi Takashi (Tokyo JPX) Yasui Sunao (Tokyo JPX), Method of making multi-layer printed wiring boards.
    상세보기
  4. Voss Forrest L. (Cedar Rapids IA) Witherell Donald R. (Cedar Rapids IA), Method of manufacture of a wiring board.
    상세보기
  5. Takahashi Akio (Hitachiota JPX) Shimazaki Takeshi (Hitachi JPX) Wajima Motoyo (Hitachi JPX) Morishita Hirosada (Hitachi JPX), Multi-layer printed circuit board and process for production thereof.
    상세보기
  6. Del Joseph A. (16326 Barneston St. Granada Hills CA 91344), Process for making multi-layer printed circuit boards, and the article resulting therefrom.
    상세보기

이 특허를 인용한 특허 (99) 인용/피인용 타임라인 분석

  1. Selna Erich (Mountain View CA), Ball grid array package for a integrated circuit.
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  3. O'Bryan, Jr., Nelson B., Capacitor having epoxy dielectric layer cured with aminophenylfluorenes.
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  4. McKinzie, III, William E.; Rogers, Shawn D., Circuit and method for suppression of electromagnetic coupling and switching noise in multilayer printed circuit boards.
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  5. McKinzie, III,William E.; Rogers,Shawn D., Circuit and method for suppression of electromagnetic coupling and switching noise in multilayer printed circuit boards.
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  6. Sugane, Mitsuhiko; Matsui, Akiko; Mukoyama, Takahide; Yamada, Tetsuro; Hiroshima, Yoshiyuki; Choraku, Kohei, Circuit board and method of manufacturing the same.
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  7. Goergen, Joel R., Circuit board through-hole impedance tuning using clearance size variations.
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  8. Steigerwald Todd W. ; Sebring Mitchell C., Circuit board voltage plane impedance matching.
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  9. Wan,Lixi, Design of low inductance embedded capacitor layer connections.
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  11. Hartman, William F.; Slenes, Kirk M.; Law, Kristen J., Dielectric material including particulate filler.
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  14. Mruz, John, Electronic component and method of making.
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  46. Sasaki, Masayuki, Method of making multilayer circuit board.
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  47. Oh, Chang Gun; Park, Ho Sik; Bae, Tae Kyun, Method of manufacturing printed circuit board.
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  48. Kim, Jin Cheol; Kim, Min Soo; Oh, Jun Rok; Kim, Tae Kyoung, Method of manufacturing printed circuit board including embedded capacitors.
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  52. Cheng, Yu-Chiang, Multi-layer circuit board.
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  56. Cheng,Yu Chiang, Multi-layer circuit board having signal, ground and power layers.
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  60. Kobayashi Naoki,JPX, Multilayer wiring board.
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