초록 ▼

The testing circuit for testing internal nodes of a device includes storage for storing the test addresses of selected internal nodes in the device. A decoder responds to a test command from a microprocessor for selecting the test addresses from the storage and supplies the test addresses to an addr

The testing circuit for testing internal nodes of a device includes storage for storing the test addresses of selected internal nodes in the device. A decoder responds to a test command from a microprocessor for selecting the test addresses from the storage and supplies the test addresses to an address bus in place of other addresses supplied to the address bus. A test decoder responds only to the test addresses on the address bus for enabling the transfer of data between the selected internal nodes in the data bus for testing the selected internal nodes.

대표청구항 ▼

In an integrated circuit device having internal data and address buses respectively connectable to external data and address buses, and having normally accessible internal nodes addressable by normal addresses from the external address bus, the improvement comprising a test mode means (100, 111, 121

In an integrated circuit device having internal data and address buses respectively connectable to external data and address buses, and having normally accessible internal nodes addressable by normal addresses from the external address bus, the improvement comprising a test mode means (100, 111, 121) in the integrated circuit device for enabling external access of predetermined and normally inaccessible internal test nodes in the integrated circuit device, said test mode means comprising: a test mode decode means (103) responsive to an address from the external address bus for outputting a control signal to set the integrated circuit device in either a normal state or a test mode state, the normal state resulting from the address being one of the normal addresses and the test mode state resulting from the address being a predetermined address for initiating a test mode; a test mode control register means (105) for storing an address of a predetermined internal test node, said address being obtainable from the external data bus; a multiplexer means (101) responsive to the control signal for connecting the internal address bus (102) to the external address bus for receiving the normal addresses when in the normal state, and connecting to the test mode control register means for receiving the address of a predetermined internal test node when in the test mode state; and test node decoder means (111, 121) responsive to the control signal and the address of the predetermined internal test node for enabling the transfer of test data from the predetermined internal test node to the internal data bus, thereby allowing the normally inaccessible test node to be accessible from outside the device.