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A single port dual RAM comprising, on a single chip, at least one storage array including a plurality of hierarchical bit lines which serve as the interconnecting path between dynamic type storage elements for main memory and static type storage elements for cache memory. Each of said storage array(

A single port dual RAM comprising, on a single chip, at least one storage array including a plurality of hierarchical bit lines which serve as the interconnecting path between dynamic type storage elements for main memory and static type storage elements for cache memory. Each of said storage array(s) includes an input/output port for selective access to the storage array. Each hierarchical bit line includes a DRAM bit line, a SRAM bit line and interface means for electrically interconnecting the DRAM bit line to the SRAM bit line or isolating the DRAM bit line from the SRAM bit line. A SPDRAM chip which shares typical DRAM peripheral circuitry may be employed in a distributed on-chip cache to enlarge the data transfer width in a simple structure.

대표청구항 ▼

In a semiconductor memory device comprising one or more than one storage array, each of said storage array(s) including a plurality of bit lines, and an input/output port connected to said plurality of bit lines by gate means for access to said storage array, wherein each of said bit lines comprisin

In a semiconductor memory device comprising one or more than one storage array, each of said storage array(s) including a plurality of bit lines, and an input/output port connected to said plurality of bit lines by gate means for access to said storage array, wherein each of said bit lines comprising: one or more than one DRAM bit line, each of said DRAM bit line(s), including a plurality of dynamic type storage elements, each of said dynamic type storage elements having a storage capacitor means for storing data in a binary state; a SRAM bit line including one or more than one static type storage element, each of said static type storage element(s) having a storage flip flop means for storing data in a binary state; and an interface means for electrically interconnecting one of said DRAM bit line(s) to said SRAM bit line or isolating said DRAM bit line(s) from said SRAM bit line.