초록 ▼

A single stage multi-rate finite impulse response filter is used as the decimating filter for a sigma-delta analog-to-digital converter. The filter uses 2048 22-bit coefficient values to produce a sampled data output signal having a sampling rate of 48 KHz and a sample resolution of 16 bits from an

A single stage multi-rate finite impulse response filter is used as the decimating filter for a sigma-delta analog-to-digital converter. The filter uses 2048 22-bit coefficient values to produce a sampled data output signal having a sampling rate of 48 KHz and a sample resolution of 16 bits from an input signal having a sampling rate of 3.072 MHz and a sample resolution of one bit. The filter uses a single read-only memory to hold the 2048 coefficient values. The coefficient values are distributed to eight four-way multiplexed accumulators by a circuitry which includes a signal multiplexer and a barrel shifter. The accumulators use unsigned arithmetic to calculate the output sample values. A value C0, representing a normalizing offset and gain applied to each of the coefficient values, is selected such that 2048 times C0 is a value which overflows the accumulator, leaving a value of zero in the accumulator.

대표청구항 ▼

A filtering system for processing a sampled data input signal, comprising: memory means for holding Q coefficient values representing a single impulse response and for providing N of said coefficient values at a plurality of output ports, where Q and N are integers; a plurality of processing means,

A filtering system for processing a sampled data input signal, comprising: memory means for holding Q coefficient values representing a single impulse response and for providing N of said coefficient values at a plurality of output ports, where Q and N are integers; a plurality of processing means, including gating means and an accumulator, for combining said input signal with P of said N coefficient values to generate R filtered output signals, where P and R are integers; means for combining said R filtered output signals to generate a single filtered output signal; distributing means, including a barrel shifter, coupled to said memory means and responsive to a control signal for distributing P of said N coefficient values to said plurality of processing means in a correspondence determined by said control signal; and control means coupled to said distributing means for generating said control signal to change the correspondence between said P coefficient values and said plurality of processing means.