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Coplanar packaging techniques for multichip circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/56
출원번호 US-0208058 (1988-06-17)
발명자 / 주소
  • Black Jerry G. (Lincoln MA) Astolfi David K. (Littleton MA) Doran Scott P. (Wakefield MA) Ehrlich Daniel J. (Lexington MA)
출원인 / 주소
  • Massachusetts Institute of Technology (Cambridge MA 02)
인용정보 피인용 횟수 : 25  인용 특허 : 9

초록

A method for assembling and interconnecting large, high-density circuits from separately fabricated components, where conventional preassembly device testing, and conventional production techniques, can be employed in an uncomplicated process. A plurality of semiconductor chips are applied connectio

대표청구항

A method for assembling and interconnecting a plurality of separately fabricated semiconductor chips comprising the steps of: (a) applying a plurality of semiconductor chips, connection-side down, to a soluble substrate; (b) encapsulating the product of step (a) on the side of said substrate to whic

이 특허에 인용된 특허 (9)

  1. Roche Georges (Chatillon Sous Bagneux FRX) Lantaires Jacques (Verrieres Le Buisson FRX), Method for encapsulating semiconductor components using temporary substrates.
  2. Argentini Dino E. (Danvers MA), Method for forming an insulator having a conductive surface.
  3. Wilson Arthur M. (Richardson TX), Method for producing an integrated circuit product having a polyimide film interconnection structure.
  4. Heiss ; Jr. John Herbert (Bethlehem PA) Schoen Joel Mark (Freehold NJ), Method for selective encapsulation.
  5. Ohuchi Masayuki (Tokyo JPX) Oodaira Hirosi (Chigasaki JPX) Yoshida Kenichi (Tokyo JPX), Method of manufacturing a circuit module.
  6. Deutscher Siegfried G. (Herzlia ILX) Grunbaum Enrique (Kfar Saba ILX), Method of producing monocrystalline semiconductor films utilizing an intermediate water dissolvable salt layer.
  7. Antypas George A. (Palo Alto CA), Process for making III-V devices.
  8. Hokuyou Shigeru (Itami JPX), Process for manufacturing a solar cell device.
  9. Hasegawa Shinichi (Tsuchiura JPX) Fujita Hisanori (Tsuchiura JPX), Process for manufacturing a vapor phase epitaxial wafer of compound semiconductor without causing breaking of wafer by u.

이 특허를 인용한 특허 (25)

  1. Xu, Jianwen; Gong, Zhiwei; Hayes, Scott M., Back side alignment structure and manufacturing method for three-dimensional semiconductor device packages.
  2. Nishiyama, Kazuo, Chip-like electronic components, a method of manufacturing the same, a pseudo wafer therefor and a method of manufacturing thereof.
  3. Nishiyama, Kazuo; Ozaki, Hiroshi; Takaoka, Yuji; Hirayama, Teruo, Chip-like electronic components, a method of manufacturing the same, a pseudo wafer therefor and a method of manufacturing thereof.
  4. Fay,Owen R.; Amrine,Craig S.; Lish,Kevin R., Die encapsulation using a porous carrier.
  5. McBride Donald G., Direct attachment of silicon chip to circuit carrier.
  6. Horton Raymond Robert ; Lanzetta Alphonso Philip ; Milewski Joseph Maryan ; Mok Lawrence S. ; Montoye Robert Kevin ; Shaukatulla Hussain, Electronic package with interconnected chips.
  7. Andros Frank E. (Binghamton NY) Bupp James R. (Endwell NY) DiPietro Michael (Vestal NY) Hammer Richard B. (Apalachin NY), Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device.
  8. Andros Frank Edward ; Bupp James Russell ; DiPietro Michael ; Hammer Richard Benjamin, Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device.
  9. Lytle,William H.; Amrine,Craig S., Flexible carrier and release method for high volume electronic package fabrication.
  10. Lytle, William H.; Amrine, Craig S., Flexible carrier for high volume electronic package fabrication.
  11. Klinker Thomas S., Indented portion of a processor package cover plate.
  12. Klinker Thomas S., Indented portion of a processor package cover plate.
  13. Degani Yinon ; Dudderar Thomas Dixon ; Tai King Lien, Method for assembling multichip modules.
  14. Olivier Brunet FR; Didier Elbaz FR; Bernard Calvas FR; Philippe Patrice FR, Method for protecting an integrated circuit chip.
  15. Xu, Jianwen; Hayes, Scott M.; Lytle, William H., Method for releasing a microelectronic assembly from a carrier substrate.
  16. Horton Raymond Robert ; Lanzetta Alphonso Philip ; Milewski Joseph Maryan ; Mok Lawrence S. ; Montoye Robert Kevin ; Shaukatulla Hussain, Method of fabricating an electronic package with interconnected chips.
  17. McCann, Carl D., Method of fabricating integrated circuit pack trays using modules.
  18. Tsuchiaki Masakatsu,JPX ; Nakasaki Yasushi,JPX ; Nishiyama Akira,JPX ; Oowaki Yukihito,JPX ; Nishino Hirotaka,JPX, Method of manufacturing a semiconductor device by detachably mounting substrates to a holder board.
  19. Lytle, William H.; Fay, Owen R.; Xu, Jianwen, Method of packaging an integrated circuit die.
  20. Goller, Bernd; Hagen, Robert Christian; Ofner, Gerald; Stuempfl, Christian; Wein, Stefan; Wörner, Holger, Method of producing a universal semiconductor housing with precrosslinked plastic embedding compounds.
  21. Xu, Jianwen, Packaging an integrated circuit die using compression molding.
  22. Tsuji Kazuto,JPX ; Yoneda Yoshiyuki,JPX ; Sakoda Hideharu,JPX ; Sono Michio,JPX ; Yamaguchi Ichiro,JPX ; Hamano Toshio,JPX ; Kubota Yoshihiro,JPX ; Hayakawa Michio,JPX ; Ikemoto Yoshihiko,JPX ; Saigo, Process for manufacturing a packaged semiconductor having a divided leadframe stage.
  23. Meyer,Thorsten; Frankowsky,Gerd; Hedler,Harry; Vasquez,Barbara; Irsigler,Roland, Process for producing a component module.
  24. Fay,Owen R.; Lish,Kevin R.; Mitchell,Douglas G., Semiconductor device packaging.
  25. Mitchell Craig ; Distefano Thomas H., System for encapsulating microelectronic devices.
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