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Semiconductor device having an improved bonding pad 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-029/04
  • H01L-029/44
출원번호 US-0513973 (1990-04-24)
우선권정보 JP-0105912 (1989-04-27)
발명자 / 주소
  • Mori, Seiichi
출원인 / 주소
  • Kabushiki Kaisha Toshiba
대리인 / 주소
    Finnegan, Henderson, Farabow, Garrett, and Dunner
인용정보 피인용 횟수 : 50  인용 특허 : 9

초록

A polysilicon film is formed on an Si substrate through an insulating oxide film, and a composite film constituted by oxide and nitride films is formed on the polysilicon film. A polycide layer is formed on the composite film, and a metal electrode layer serving as a bonding pad is formed on the pol

대표청구항

1. A semiconductor device comprising: a semiconductor substrate; a first insulating layer formed on said semiconductor substrate; a polysilicon film formed on said first insulating layer; a second insulating layer formed on said polysilicon film, said second insulating layer including a compos

이 특허에 인용된 특허 (9)

  1. Crowder Billy L. (Putnam Valley NY) Reisman Arnold (Yorktown Heights NY), Doped polysilicon silicide semiconductor integrated circuit interconnections.
  2. Thibault Louis R. (Piscataway NJ) Yau Leopoldo D. (New Providence NJ), Fabrication of small contact openings in large-scale-integrated devices.
  3. Levinstein Hyman J. (Berkeley Heights NJ) Murarka Shyam P. (New Providence NJ) Sinha Ashok K. (New Providence NJ), Integrated semiconductor circuit structure and method for making it.
  4. Okamoto Tatsuo (Itami JPX) Kotani Hideo (Itami JPX) Oono Takio (Itami JPX) Watabe Kiyoto (Itami JPX) Kinoshita Yasushi (Itami JPX) Nishikawa Yoshikazu (Itami JPX), Interconnection structure in semiconductor device and manufacturing method of the same.
  5. Lehrer William I. (Los Altos CA), Multilayer metal silicide interconnections for integrated circuits.
  6. Yoshikawa Kuniyoshi (Tokyo JPX), Non-volatile semiconductor memory device and method of the manufacture thereof.
  7. Mohsen Amr M. (Saratoga CA) Hamdy Esmat Z. (Fremont CA) McCullum John L. (Saratoga CA), Programmable low impedance anti-fuse element.
  8. Abe Masahiro (Yokohama JPX) Aoyama Masaharu (Fujisawa JPX) Ajima Takashi (Kamakura JPX) Yonezawa Toshio (Yokosuka JPX), Semiconductor device with an improved bonding section.
  9. Kosa Yasunobu (Kodaira JPX) Shimizu Shinji (Koganei JPX), Semiconductor memory device and a method of manufacturing the same.

이 특허를 인용한 특허 (50)

  1. Zamanian Mehdi, Barrier and landing pad structure in an integrated circuit.
  2. Young-hoon Park KR; Eun-young Min KR; Weon-cheol Hong KR, Bonding pad structures for semiconductor devices and fabrication methods thereof.
  3. Yin, Zhiping; Iyer, Ravi; Glass, Thomas R.; Holscher, Richard; Niroomand, Ardavan; Somerville, Linda K.; Sandhu, Gurtej S., Circuitry and gate stacks.
  4. Skala Stephen L. ; Bothra Subhas ; Pramanik Dipu ; Shu William Kuang-Hua, Composite metallization structures for improved post bonding reliability.
  5. Li,Weimin; Yin,Zhiping, Compositions of matter and barrier layer compositions.
  6. Nguyen Loi N. ; Bryant Frank R. ; Balasinski Artur P., Dual landing pad structure in an integrated circuit.
  7. Chan Tsiu C. ; Bryant Frank R. ; Nguyen Loi N. ; Balasinski Artur P., Dual landing pad structure including dielectric pocket.
  8. Bothra Subhas ; Skala Stephen L. ; Pramanik Dipu, Electromigration impeding composite metallization lines and methods for making the same.
  9. Haga, Motoharu; Yasuda, Kaoru; Nii, Akinori; Nishiyama, Yuto, Electronic device.
  10. Cave Nigel G. ; Yu Kathleen C. ; Farkas Janos, Integrated circuit having a support structure.
  11. Li,Weimin; Yin,Zhiping; Budge,William, Low K interlevel dielectric layer fabrication methods.
  12. Li, Weimin; Yin, Zhiping; Budge, William, Low k interlevel dielectric layer fabrication methods.
  13. Li,Weimin; Yin,Zhiping; Budge,William, Low k interlevel dielectric layer fabrication methods.
  14. Cave Nigel G. ; Yu Kathleen C. ; Farkas Janos, Method for forming a semiconductor device.
  15. Zamanian Mehdi (Carrollton TX), Method of forming a barrier and landing pad structure in an integrated circuit.
  16. Chan Tsiu C. (Carrollton TX) Bryant Frank R. (Denton TX) Nguyen Loi N. (Carrollton TX), Method of forming a landing pad structure in an integrated circuit.
  17. Chan Tsiu C. ; Bryant Frank R. ; Nguyen Loi N., Method of forming a landing pad structure in an integrated circuit.
  18. Chan Tsiu C. ; Bryant Frank R. ; Nguyen Loi N., Method of forming a landing pad structure in an integrated circuit.
  19. Nguyen Loi N. ; Bryant Frank R. ; Balasinski Artur P., Method of forming a landing pad structure in an integrated circuit.
  20. Miller Robert Otis ; Smith Gregory Clifford, Method of forming a landing pad sturcture in an integrated circuit.
  21. Nguyen Loi N. ; Bryant Frank R., Method of forming a metal contact to landing pad structure in an integrated circuit.
  22. Nguyen Loi N. ; Bryant Frank R., Method of forming a metal contact to landing pad structure in an integrated circuit.
  23. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  24. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  25. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  26. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  27. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  28. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  29. Mototsugu Okushima JP, Multilayer wiring structure and semiconductor device having the same, and manufacturing method therefor.
  30. Okushima Mototsugu,JPX, Multilayer wiring structure and semiconductor device having the same, and manufacturing method therefor.
  31. Holscher, Richard; Yin, Zhiping; Glass, Tom, Semiconductor constructions.
  32. Holscher, Richard; Yin, Zhiping; Glass, Tom, Semiconductor constructions having antireflective portions.
  33. Kazutaka Otsuki JP, Semiconductor device.
  34. Semi, Atsushi, Semiconductor device and fabrication method thereof.
  35. Kenji Tabaru JP; Kazunori Yoshikawa JP; Takahiro Yokoi JP; Akemi Teratani JP, Semiconductor device and manufacturing method thereof.
  36. Kim, Shin; Chung, Tae-Gyeong; Kim, Nam-Seog; Lee, Woo-Dong; Lee, Jin-Hyuk, Semiconductor device bonding pad resistant to stress and method of fabricating the same.
  37. Ishio, Seiichiro; Suzuki, Yasutoshi, Semiconductor device having bonding pads and probe pads.
  38. Kurihara, Toshimichi; Toda, Tetsu; Tsubaki, Shigeki, Semiconductor device with an improved bonding pad structure and method of bonding bonding wires to bonding pads.
  39. Holscher, Richard; Yin, Zhiping; Glass, Tom, Semiconductor devices having antireflective material.
  40. Li, Weimin; Yin, Zhiping, Semiconductor devices, and semiconductor processing methods.
  41. Holscher, Richard; Yin, Zhiping; Glass, Tom, Semiconductor processing methods.
  42. Sandhu,Gurtej S.; Sharan,Sujit, Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks.
  43. DeBoer, Scott Jeffrey; Moore, John T., Semiconductor processing methods of transferring patterns from patterned photoresists to materials.
  44. DeBoer, Scott Jeffrey; Moore, John T., Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride.
  45. DeBoer,Scott Jeffrey; Moore,John T., Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride.
  46. DeBoer,Scott Jeffrey; Moore,John T., Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride.
  47. DeBoer,Scott Jeffrey; Moore,John T., Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride.
  48. Gao, Guilian; Lewis, David John; Murphy, Stephen Thomas, Solder pad structure for low temperature co-fired ceramic package and method for making the same.
  49. DeBoer,Scott Jeffrey; Moore,John T., Structures comprising a layer free of nitrogen between silicon nitride and photoresist.
  50. Anschel Morris (Wappingers Falls NY) Ormond Douglas W. (Wappingers Falls NY) Hayunga Carl P. (Poughkeepsie NY), Thin film metallization process for improved metal to substrate adhesion.
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