초록 ▼

A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS

A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to a combination of an FM modulator and FM demodulator to provide a delay circuit for an analog circuit.

대표청구항 ▼

A signal delay circuit for delaying analog signals comprising: (a) frequency modulation means for receiving an analog signal to be delayed, performing a pulse frequency-modulation operation using the analog signal to provide a frequency-modulated pulse signal whose frequency corresponds to the value

A signal delay circuit for delaying analog signals comprising: (a) frequency modulation means for receiving an analog signal to be delayed, performing a pulse frequency-modulation operation using the analog signal to provide a frequency-modulated pulse signal whose frequency corresponds to the value of the analog signal, and outputting the frequency-modulated pulse signal; (b) signal delay means for receiving and delaying the pulse signal, the signal delay means including: i) CMOS gate circuit means having an input terminal to which the pulse signal is applied, an output terminal from which a delayed pulse signal is derived, and power voltage supply terminals to which operation power voltages are applied; ii) voltage control means, located in a power supply path for the CMOS gate circuit means, for controlling the power voltage applied to the CMOS gate circuit means in response to a control signal thereby to control the amount of delay imparted to the pulse signal; and iii) means for providing the control signal to the voltage control means; and (c) frequency demodulation means for receiving the delayed pulse signal and pulse frequency-demodulating the received signal, the output signal of said frequency demodulation means constituting a delayed analog signal corresponding to the analog input signal.