초록 ▼

Method and apparatus providing a programmable logic device which has a high level subroutine stack element and a random access memory suitable for control applications. The method utilizes high level constructs bearing a one-to-one relationship to the architecture of the apparatus so that the design

Method and apparatus providing a programmable logic device which has a high level subroutine stack element and a random access memory suitable for control applications. The method utilizes high level constructs bearing a one-to-one relationship to the architecture of the apparatus so that the design of the controller is facilitated resulting in a rapidly-executed program which is easy to comprehend, verify and document. Subroutines are readily implemented by the controller by virtue of its last-in, first-out stack and a state counter which allow the contents of the counter to be “pushed”onto the stack upon invocation of the subroutine and “popped”from the stack upon return from the subroutine. Provision of the random access memory allows the controller to store information supplied from an external device, such as a central processing unit. The operation of the controller can be readily modified according to the control information stored in the memory by use of a high level language RAMREAD construct. The random access memory also provides scratch pad capability for the controller so that information written to a memory location, under control of a programmable OR array, can be used as a separate, independent counting and timing channel, in an exemplary application. The stack and/or the random access memory are suitable for inclusion in a controller of either a programmable logic array (PLA-), programmable array logic (PAL-), or a programmable read-only-memory (PROM-) based design.

대표청구항 ▼

A logic device having a plurality of external terminals and a plurality of input/output ports, comprising: programmable array means responsive to signals applied to said external terminals of said device for generating a plurality of logic signals; a plurality of programmable output cell means, each

A logic device having a plurality of external terminals and a plurality of input/output ports, comprising: programmable array means responsive to signals applied to said external terminals of said device for generating a plurality of logic signals; a plurality of programmable output cell means, each receiving one of said logic signals, for storing predetermined ones of said logic signals, and for generating a signal therefrom at a predetermined one of said input/output ports; a plurality of storage cell means, each receiving one of said logic signals, for storing predetermined ones of said logic signals and for generating a signal therefrom; counter means, receiving at least one of said logic signals, for storing a count value therefrom, for selectably incrementing or decrementing said count value, and for generating therefrom counting signals indicative of said count value; and means receiving said counting signals and at least one of said logic signals, for selectably storing said count value in a last-in, first-out stack, for removing the last-in contents of said stack, and for generating therefrom signals indicative of said last-in contents; said counter means also receiving said signals generated by said stack means.