초록 ▼

A readout circuit for use with a focal plane array that employs a single transistor in each unit cell and a single capacitive feedback transimpedance amplifier to process the outputs of each column of detector elements of the array. The capacitive feedback transimpedance amplifiers extract the signa

A readout circuit for use with a focal plane array that employs a single transistor in each unit cell and a single capacitive feedback transimpedance amplifier to process the outputs of each column of detector elements of the array. The capacitive feedback transimpedance amplifiers extract the signals associated with the pixels along a particular row of the array. The present invention permits high performance readouts to be constructed with very little circuitry in the unit cells. Only a single minimum sized transistor switch is required in each unit cell to perform readout and reset functions for the array. In the disclosed embodiment, the readout circuit comprises an array of unit cells, each cell comprising a detector input circuit, a single transistor and a single charge storage capacitor. Row address circuits are coupled to the cells in each row of the array. A plurality of capacitive feedback transimpedance amplifiers are coupled to the cells in each column of the array. The amplifiers process charge derived from the detector elements and stored in the charge storage capacitor of each unit cell. Column multiplexing circuits multiplex the output signals provided by each of the amplifiers. Column address circuits are coupled to the column multiplexing circuits which couple output signals from each of the multiplexer circuits as the output from the readout circuit.

대표청구항 ▼

Focal plane array readout circuit for use with a focal plane array having a predetermined number of rows and columns of detector elements, said readout circuit comprising: an array of unit cells, each cell comprising a detector input circuit, a single transistor and a single charge storage capacitan

Focal plane array readout circuit for use with a focal plane array having a predetermined number of rows and columns of detector elements, said readout circuit comprising: an array of unit cells, each cell comprising a detector input circuit, a single transistor and a single charge storage capacitance; a plurality of row address circuits respectively coupled to respective gates of the transistors in a selected row of unit cells of the array; a plurality of capacitive feedback transimpedance amplifiers equal to the number of columns of detector elements, each capacitive feedback transimpedance amplifier coupled to the transistors in a selected column of unit cells of the array for processing charge stored in the charge storage capacitance of each unit cell of a selected row of the unit cells in parallel; a plurality of column multiplexing circuits coupled to respective ones of the capacitive feedback transimpedance amplifiers for multiplexing output signals provided by each of the amplifiers; and a plurality of column address circuits respectively coupled to the column multiplexing circuits for addressing each of the plurality of column multiplexing circuits for coupling output signals provided by each of the multiplexer circuits as the focal plane array output from the readout circuit.