이 특허를 인용한 특허 (86)

1. Farber, David A.; Lachman, Ronald D., Accessing data in a data processing system.

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2. Blandy, Geoffrey Owen, Apparatus and method for an enhanced integer divide in an IA64 architecture.

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3. Blandy, Geoffrey Owen; Johnson, Andrew, Apparatus and method for avoiding deadlocks in a multithreaded environment.

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4. Blandy, Geoffrey Owen, Apparatus and method for creating instruction bundles in an explicitly parallel architecture.

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5. Blandy, Geoffrey Owen; Johnson, Andrew; Shi, Danling, Apparatus and method for creating instruction groups for explicity parallel architectures.

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6. Blandy, Geoffrey Owen, Apparatus and method for detecting and handling exceptions.

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7. Fisher Jeffes,Timothy, Apparatus and method for generating a code mask.

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8. Agarwal, Anant, Architecture and programming in a parallel processing environment with switch-interconnected processors.

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9. Luick David Arnold, Branch history cache.

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10. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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11. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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12. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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13. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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14. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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15. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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16. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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17. Agarwal, Anant; Bratt, Ian R.; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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18. Agarwal, Anant; Bratt, Ian Rudolf; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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19. Agarwal, Anant; Bratt, Ian Rudolf; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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20. Agarwal, Anant; Mattina, Matthew, Caching in multicore and multiprocessor architectures.

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21. Lee, Douglas; Fouxman, Eugene; Krepner, Shlomi; Roy, Andrew; Bakshi, Amit; Karpov, Dmitry, Code editing for data traffic modification.

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22. Hampapuram Hari ; Lee Yen C. ; Ang Michael ; Jacobs Eino, Compiler generating swizzled instructions usable in a simplified cache layout.

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23. Jacobs Eino ; Ang Michael, Compressed Instruction format for use in a VLIW processor.

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24. Jacobs, Eino; Ang, Michael, Compressed instruction format for use in a VLIW processor.

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25. Jacobs, Eino; Ang, Michael, Compressed instruction format for use in a VLIW processor.

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26. Hampapuram Hari ; Lee Yen C ; Jacobs Eino ; Ang Michael, Compressed instruction format for use in a VLIW processor and processor for processing such instructions.

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27. Lekatsas,Haris; Henkel,Joerg; Chakradhar,Srimat; Jakkula,Venkata, Compressed memory architecture for embedded systems.

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28. Roberts James S., Compressing variable-length instruction prefix bytes.

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29. Farber, David A.; Lachman, Ronald D., Computer file system using content-dependent file identifiers.

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30. Denman Paul W.,GB3, Computer system for executing instruction stream containing mixed compressed and uncompressed instructions by automatic.

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31. Farber, David A.; Lachman, Ronald D., Controlling access to data in a data processing system.

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32. Asato Akira,JPX, Data processing device having a variable length code processing mechanism.

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33. Iwata Yasushi,JPX ; Asato Akira,JPX, Data processing device to compress and decompress VLIW instructions by selectively storing non-branch NOP instructions.

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34. Farber David A. ; Lachman Ronald D., Data processing system using substantially unique identifiers to identify data items, whereby identical data items hav.

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35. Grundmann, William J.; Uhler, George M.; Calcagni, Richard E., Digital processor with bit mask for counting registers for fast register saves.

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36. Lekatsas,Haris; Henkel,Joerg; Chakradhar,Srimat; Jakkula,Venkata, Dynamic content-aware memory compression and encryption architecture.

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37. Dasgupta Ranjan (Naperville IL), Dynamic hashing method for optimal distribution of locks within a clustered system.

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38. Farber, David A.; Lachman, Ronald D., Enforcement and policing of licensed content using content-based identifiers.

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39. Miller Paul K., Expanding instructions with variable-length operands to a fixed length.

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40. Rose, Anthony, Filter for a distributed network.

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41. Rose, Anthony, Filter for a distributed network.

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42. Rose, Anthony, Filter for a distributed network.

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43. Mahalingaiah Rupaka, Forcing regularity into a CISC instruction set by padding instructions.

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44. Katsura,Koyo; Kojima,Shinichi; Kurakami,Noriyuki, Graphic processing apparatus utilizing improved data transfer to reduce memory size.

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45. Sachs,Howard G.; Arya,Siamak, Instruction cache association crossbar switch.

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46. Howard G. Sachs ; Siamak Arya, Instruction cache associative crossbar switch.

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47. Miller Richard G. ; Cardillo Louis A. ; Mathieson John G. ; Smith Eric R., Instruction compression and decompression system and method for a processor.

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48. Johnson, Stephen C., Instruction packing for an advanced microprocessor.

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49. Wentzlaff, David M.; Mattina, Matthew; Agarwal, Anant, Managing cache memory in a parallel processing environment.

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50. Wentzlaff, David; Mattina, Matthew; Agarwal, Anant, Managing cache memory in a parallel processing environment.

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51. Wentzlaff, David; Mattina, Matthew; Agarwal, Anant, Managing cache memory in a parallel processing environment.

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52. Kim, Donglok; Berg, Stefan G.; Sun, Weiyun; Kim, Yongmin, Method and apparatus for compressing VLIW instruction and sharing subinstructions.

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53. Kim,Donglok; Berg,Stefan G.; Sun,Weiyun; Kim,Yongmin, Method and apparatus for compressing VLIW instruction and sharing subinstructions.

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54. Vondran, Jr., Gary L, Method and apparatus for efficient cache mapping of compressed VLIW instructions.

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55. Sakhin Yuli Kh.,RUX ; Artyomov Alexander M.,RUX ; Lizorkin Alexey P.,RUX ; Rudometov Vladimir V.,RUX ; Nazarov Leonid N.,RUX, Method and apparatus for packing and unpacking wide instruction word using pointers and masks to shift word syllables to.

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56. Faraboschi Paolo ; Fisher Joseph A., Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition.

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57. Rozas, Guillermo; Klaiber, Alexander; Hao, Eric, Method and system for using one or more address bits and an instruction to increase an instruction set.

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58. Faraboschi Paolo ; Raje Prasad, Method for storing and decoding instructions for a microprocessor having a plurality of function units.

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59. Ussery Cary ; Levia Oz ; Ryan Raymond, Method of generating application specific integrated circuits using a programmable hardware architecture.

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60. Pechanek Gerald G. ; Barry Edwin F. ; Revilla Juan Guillermo ; Larsen Larry D., Methods and apparatus for scalable instruction set architecture with dynamic compact instructions.

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61. Banning,John P.; Anvin,H. Peter; Rozas,Guillermo J., Methods and systems for maintaining information for locating non-native processor instructions when executing native processor instructions.

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62. Kiyokazu Nishioka JP; Kazuhiko Tanaka JP; Yoshifumi Fujikawa JP; Toru Nojiri JP; Keiji Kojima JP; Koichi Terada JP; Yoshiki Kurokawa JP; Koji Hosoki JP, Parallel computing units having special registers storing large bit widths.

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63. Ang Michael ; Jacobs Eino, Planar cache layout and instruction stream therefor.

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64. Topham,Nigel Peter, Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned im.

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65. Topham,Nigel Peter, Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions.

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66. Nishioka, Kiyokazu; Tanaka, Kazuhiko; Fujikawa, Yoshifumi; Nojiri, Toru; Kojima, Keiji; Terada, Koichi; Kurokawa, Yoshiki; Hosoki, Koji, Processor including a plurality of computing devices.

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67. Hussain, Zahid, Processor instruction including option bits encoding which instructions of an instruction packet to execute.

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68. Hull James M. ; Fielden Kent ; Mulden Hans ; Sharangpani Harshvardhan, Processor utilizing a template field for encoding instruction sequences in a wide-word format.

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69. Vasekin,Vladimir; Rose,Andrew Christopher, Program instruction decompression and compression techniques.

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70. Luick Dave A. ; Kiefer Kenneth J. ; Kunkel Steve R. ; Winterfield Philip B., Pseudo zero cycle address generator and fast memory access.

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71. Ebeling,Christopher D., Queuing and aligning data.

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72. Dasgupta Ranjan (Naperville IL), Reliable datagram service provider for fast messaging in a clustered environment.

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73. Banning, John P.; Hao, Eric; Coon, Brett, System and method of instruction modification.

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74. Banning, John P.; Hao, Eric; Coon, Brett, System and method of instruction modification.

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75. Banning, John; Hao, Eric; Coon, Brett, System and method of instruction modification.

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76. Guffens,Jan; Callewaert,Ludwig; Van Nieuwenhove,Koenraad, System for processing VLIW words containing variable length instructions having embedded instruction length identifiers.

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77. Chan Stephen H. (Sunnyvale CA), Technique for accelerating instruction decoding of instruction sets with variable length opcodes in a pipeline microproc.

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78. Paul K. Miller, Using padded instructions in a block-oriented cache.

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79. Rupaka Mahalingaiah, Using separate caches for variable and generated fixed-length instructions.

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80. Luick David A. ; Winterfield Philip B., VLIW architecture and method for expanding a parcel.

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81. Slavenburg Gerrit Ary (Mountain View CA) Labrousse Jean-Michel Junien (Palo Alto CA), VLIW processing device including improved memory for avoiding collisions without an excessive number of ports.

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82. Sachs, Howard G.; Arya, Siamak, VLIW processor and method therefor.

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83. Jacobs Eino ; Ang Michael, VLIW processor which processes compressed instruction format.

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84. Koga,Yoshihiro; Fujimoto,Masakazu; Matsumoto,Michihiro, Variable length decoding device and variable length decoding method and reproducing system.

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85. Luick David Arnold, Very long instruction word (VLIW) computer having efficient instruction code format.

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86. Wisniewski James J. (Bristow VA) Glave Fred E. (Great Falls VA) Sharper Craig A. (Los Altos CA), Zero byte substitution method and apparatus for telecommunications equipment.

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