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AlN and AlN-containing composites 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C04B-035/58
출원번호 US-0338019 (1989-04-14)
발명자 / 주소
  • Bolt John D. (Landenberg PA) Tebbe Frederick N. (Hockessin DE)
출원인 / 주소
  • E. I. Du Pont de Nemours and Company (Wilmington DE 02)
인용정보 피인용 횟수 : 95  인용 특허 : 0

초록

Shaped articles of polycrystalline AlN and AlN-containing composites; the AlN articles having thermal conductivities of at least about 70 W/mK (watts/meter °K); the AlN component effecting good thermal conductivity in the composited articles.

대표청구항

A shaped article in the form of a fiber of polycrystalline aluminum nitride having a thermal conductivity of at least about 70 W/mK.

이 특허를 인용한 특허 (95)

  1. Gotoh, Takeshi; Murata, Hiroshi; Ichikawa, Kohki, Aluminum nitride powder and aluminum nitride sintered compact.
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  2. Maxim, George; Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker, Backside semiconductor die trimming.
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  3. Morris, Thomas Scott; Jandzinski, David; Parker, Stephen; Chadwick, Jon; Costa, Julio C., Encapsulated dies with enhanced thermal performance.
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  4. Morris, Thomas Scott; Jandzinski, David; Parker, Stephen; Chadwick, Jon; Costa, Julio C., Encapsulated dies with enhanced thermal performance.
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  5. Morris, Thomas Scott; Jandzinski, David; Parker, Stephen; Chadwick, Jon; Costa, Julio C., Encapsulated dies with enhanced thermal performance.
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  6. Morris, Thomas Scott; Jandzinski, David; Parker, Stephen; Chadwick, Jon; Costa, Julio C., Encapsulated dies with enhanced thermal performance.
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  7. Morris, Thomas Scott; Jandzinski, David; Parker, Stephen; Chadwick, Jon; Costa, Julio C., Encapsulated dies with enhanced thermal performance.
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  8. Morris, Thomas Scott; Jandzinski, David; Parker, Stephen; Chadwick, Jon; Costa, Julio C., Encapsulated dies with enhanced thermal performance.
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  9. Morris, Thomas Scott; Jandzinski, David; Parker, Stephen; Chadwick, Jon; Costa, Julio C., Encapsulated dies with enhanced thermal performance.
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  10. Morris, Thomas Scott; Jandzinski, David; Parker, Stephen; Chadwick, Jon; Costa, Julio C., Encapsulated dies with enhanced thermal performance.
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  11. Costa, Julio C.; Morris, Thomas Scott; Hammond, Jonathan Hale; Jandzinski, David; Parker, Stephen; Chadwick, Jon, Flip chip module with enhanced properties.
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  12. Costa, Julio C.; Morris, Thomas Scott; Hammond, Jonathan Hale; Jandzinski, David; Parker, Stephen; Chadwick, Jon, Flip chip module with enhanced properties.
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  13. Costa, Julio C.; Morris, Thomas Scott; Hammond, Jonathan Hale; Jandzinski, David; Parker, Stephen; Chadwick, Jon, Flip chip module with enhanced properties.
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  14. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Method for manufacturing an integrated circuit package.
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  15. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Method for manufacturing an integrated circuit package.
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  16. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Method for manufacturing an integrated circuit package.
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  17. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Method for manufacturing an integrated circuit package.
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  18. Costa, Julio C.; Shuttleworth, David M.; Antonell, Michael J., Method of manufacture for a semiconductor device.
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  19. Costa, Julio C.; Shuttleworth, David M.; Antonell, Michael J., Method of manufacture for a semiconductor device.
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  20. Costa, Julio C.; Shuttleworth, David M.; Antonell, Michael J., Method of manufacture for a semiconductor device.
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  21. Costa, Julio C.; Shuttleworth, David M.; Antonell, Michael J., Method of manufacture for a semiconductor device.
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  22. Costa, Julio C.; Shuttleworth, David M.; Antonell, Michael J., Method of manufacture for a semiconductor device.
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  23. Costa, Julio C.; Shuttleworth, David M.; Antonell, Michael J., Method of manufacture for a semiconductor device.
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  24. Costa, Julio C., Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer.
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  25. Costa, Julio C., Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer.
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  26. Costa, Julio C., Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer.
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  27. Costa, Julio C., Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer.
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  28. Leipold, Dirk Robert Walter; Maxim, George; Costa, Julio C.; Scott, Baker, Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer.
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  29. Leipold, Dirk Robert Walter; Maxim, George; Costa, Julio C.; Scott, Baker, Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer.
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  30. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  31. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  32. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  33. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  34. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  35. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  36. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  37. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  38. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  39. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  40. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  41. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  42. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Microelectronics package with inductive element and magnetically enhanced mold compound component.
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  43. Leipold, Dirk Robert Walter; Maxim, George; Costa, Julio C.; Scott, Baker, Microelectronics package with integrated sensors.
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  44. Leipold, Dirk Robert Walter; Maxim, George; Costa, Julio C.; Scott, Baker, Microelectronics package with integrated sensors.
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  45. Leipold, Dirk Robert Walter; Maxim, George; Costa, Julio C.; Scott, Baker, Microelectronics package with integrated sensors.
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  46. Leipold, Dirk Robert Walter; Maxim, George; Costa, Julio C.; Scott, Baker, Microelectronics package with integrated sensors.
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  47. Costa, Julio C.; Maxim, George, Microelectronics package with self-aligned stacked-die assembly.
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  48. Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker; Maxim, George, Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer.
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  49. Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker; Maxim, George, Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer.
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  50. Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker; Maxim, George, Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer.
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  51. Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker; Maxim, George, Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer.
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  52. Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker; Maxim, George, Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer.
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  53. Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker; Maxim, George, Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer.
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  54. Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker; Maxim, George, Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer.
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  55. Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker; Maxim, George, Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer.
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  56. Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker; Maxim, George, Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer.
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  57. Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker, Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same.
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  58. Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker, Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same.
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  59. Leipold, Dirk Robert Walter; Costa, Julio C.; Scott, Baker, Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same.
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  60. M체he,Andreas, Process for calibrating the temperature control unit of an oven and oven for carrying out this process.
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  61. Leipold, Dirk Robert Walter; Maxim, George; Scott, Baker; Costa, Julio C., Radio frequency (RF) switch.
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  62. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Semiconductor package with reduced parasitic coupling effects and process for making the same.
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  63. Jensen James A. (544 Cabot Dr. ; Hickory Hill Hockessin DE 19707), Silicon-filled aluminum polymer precursors to SiC-AlN ceramics.
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  64. Costa, Julio C.; Shuttleworth, David M.; Antonell, Michael J., Silicon-on-plastic semiconductor device and method of making the same.
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  65. Costa, Julio C.; Shuttleworth, David M.; Antonell, Michael J., Silicon-on-plastic semiconductor device and method of making the same.
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  66. Costa, Julio C.; Shuttleworth, David M.; Antonell, Michael J., Silicon-on-plastic semiconductor device and method of making the same.
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  67. Costa, Julio C., Silicon-on-plastic semiconductor device with interfacial adhesion layer.
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  68. Costa, Julio C.; Vandemeer, Jan Edward, Substrate structure with embedded layer for post-processing silicon handle elimination.
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  69. Costa, Julio C.; Vandemeer, Jan Edward, Substrate structure with embedded layer for post-processing silicon handle elimination.
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  70. Costa, Julio C.; Vandemeer, Jan Edward, Substrate structure with embedded layer for post-processing silicon handle elimination.
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  71. Costa, Julio C.; Aigner, Robert, Thermally enhanced semiconductor package and process for making the same.
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  72. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Thermally enhanced semiconductor package having field effect transistors with back-gate feature.
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  73. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Thermally enhanced semiconductor package having field effect transistors with back-gate feature.
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  74. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Thermally enhanced semiconductor package having field effect transistors with back-gate feature.
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  75. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Thermally enhanced semiconductor package having field effect transistors with back-gate feature.
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  76. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Thermally enhanced semiconductor package having field effect transistors with back-gate feature.
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  77. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker, Thermally enhanced semiconductor package having field effect transistors with back-gate feature.
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  78. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker; Hatcher, Jr., Merrill Albert; Mobley, Stephen, Thermally enhanced semiconductor package with thermal additive and process for making the same.
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  79. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker; Hatcher, Jr., Merrill Albert; Mobley, Stephen, Thermally enhanced semiconductor package with thermal additive and process for making the same.
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  80. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker; Hatcher, Jr., Merrill Albert; Mobley, Stephen, Thermally enhanced semiconductor package with thermal additive and process for making the same.
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  81. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker; Hatcher, Jr., Merrill Albert; Mobley, Stephen, Thermally enhanced semiconductor package with thermal additive and process for making the same.
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  82. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker; Hatcher, Jr., Merrill Albert; Mobley, Stephen, Thermally enhanced semiconductor package with thermal additive and process for making the same.
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  83. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker; Hatcher, Jr., Merrill Albert; Mobley, Stephen, Thermally enhanced semiconductor package with thermal additive and process for making the same.
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  84. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker; Hatcher, Jr., Merrill Albert; Mobley, Stephen, Thermally enhanced semiconductor package with thermal additive and process for making the same.
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  85. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker; Hatcher, Jr., Merrill Albert; Mobley, Stephen, Thermally enhanced semiconductor package with thermal additive and process for making the same.
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  86. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker; Hatcher, Jr., Merrill Albert; Mobley, Stephen, Thermally enhanced semiconductor package with thermal additive and process for making the same.
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  87. Costa, Julio C.; Maxim, George; Leipold, Dirk Robert Walter; Scott, Baker; Hatcher, Jr., Merrill Albert; Mobley, Stephen, Thermally enhanced semiconductor package with thermal additive and process for making the same.
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  88. Li Che-Yu (Ithaca NY), Tiled panel display assembly.
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  89. Li Che-Yu (Ithaca NY), Tiled panel display assembly.
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  90. Costa, Julio C.; Hammond, Jonathan Hale; Vandemeer, Jan Edward; Hatcher, Merrill Albert; Chadwick, Jon, Wafer-level package with enhanced performance.
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  91. Hatcher, Jr., Merrill Albert; Hammond, Jonathan Hale; Chadwick, Jon; Costa, Julio C.; Vandemeer, Jan Edward, Wafer-level package with enhanced performance.
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  92. Hatcher, Jr., Merrill Albert; Hammond, Jonathan Hale; Chadwick, Jon; Costa, Julio C.; Vandemeer, Jan Edward, Wafer-level package with enhanced performance.
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  93. Hatcher, Jr., Merrill Albert; Hammond, Jonathan Hale; Chadwick, Jon; Costa, Julio C.; Vandemeer, Jan Edward, Wafer-level package with enhanced performance.
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  94. Vandemeer, Jan Edward; Hammond, Jonathan Hale; Costa, Julio C., Wafer-level package with enhanced performance.
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  95. Vandemeer, Jan Edward; Hammond, Jonathan Hale; Costa, Julio C., Wafer-level package with enhanced performance.
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