이 특허를 인용한 특허 (197)

1. Guttag, Karl M., Allocating memory on a spatial light modulator.

   상세보기
2. Guttag, Karl M., Allocating registers on a spatial light modulator.

   상세보기
3. Guttag, Karl M., Allocation registers on a spatial light modulator.

   상세보기
4. Corr, William E., Apparatus and method for determining effect of on-chip noise on signal propagation.

   상세보기
5. Teene Andres R., Apparatus and method for testing of integrated circuits.

   상세보기
6. Daigle, Clayton; Xiao, Jinwen; Thomsen, Axel; Roy, Subrata; Wang, Xiaodong, Apparatus for mixed signal interface acquisition circuitry and associated methods.

   상세보기
7. Xiao, Jinwen; Konecny, Pavel; Thomsen, Axel; Daigle, Clayton; Wang, Xiaodong; Khoury, John; Westwick, Alan; Tadayon, Shahram, Apparatus for mixed signal interface circuitry and associated methods.

   상세보기
8. Xiao, Jinwen; Konecny, Pavel; Thomsen, Axel; Daigle, Clayton; Wang, Xiaodong; Khoury, John; Westwick, Alan; Tadayon, Shahram, Apparatus for mixed signal interface circuitry and associated methods.

   상세보기
9. Xiao, Jinwen; Konecny, Pavel; Thomsen, Axel; Daigle, Clayton; Wang, Xiaodong; Khoury, John; Westwick, Alan; Tadayon, Shahram, Apparatus for mixed signal interface circuitry and associated methods.

   상세보기
10. Chhor Khushrav S. ; Chang Bo Soon ; Lacey Timothy M., Architecture, circuitry and method for configuring volatile and/or non-volatile memory for programmable logic applications.

    상세보기
11. Liu, Zengtao T., Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells.

    상세보기
12. Guttag, Karl M.; Guttag, Alvin, Bit serial control of light modulating elements.

    상세보기
13. Gyoo-Chan Sim KR, Boundary scan cells to improve testability of core-embedded circuits.

    상세보기
14. Cox, William D., Cell architecture to reduce customization in a semiconductor device.

    상세보기
15. Becker, Scott T., Cell circuit and layout with linear finfet structures.

    상세보기
16. Becker, Scott T., Circuitry and layouts for XOR and XNOR logic.

    상세보기
17. Becker, Scott T., Circuitry and layouts for XOR and XNOR logic.

    상세보기
18. Becker, Scott T., Circuitry and layouts for XOR and XNOR logic.

    상세보기
19. Becker, Scott T.; Smayling, Michael C.; Gandhi, Dhrumil; Mali, Jim; Lambert, Carole; Quandt, Jonathan R.; Fox, Daryl, Circuits with linear finfet structures.

    상세보기
20. Smayling, Michael C.; Becker, Scott T., Coarse grid design methods and structures.

    상세보기
21. Smayling, Michael C.; Becker, Scott T., Coarse grid design methods and structures.

    상세보기
22. Smayling, Michael C.; Becker, Scott T., Coarse grid design methods and structures.

    상세보기
23. Young,Steven P., Columnar architecture.

    상세보기
24. Young, Steven P., Columnar floorplan.

    상세보기
25. Young,Steven P., Columnar floorplan.

    상세보기
26. Cox, William D., Configuring structured ASIC fabric using two non-adjacent via layers.

    상세보기
27. Abhishek, Kumar, Control signal synchronization of a scannable storage circuit.

    상세보기
28. Catalasan,Manolito M.; Rakshani,Vafa J.; Spittles,Edmund H.; Sippel,Tim; Unda,Richard, Coupling of signals between adjacent functional blocks in an integrated circuit chip.

    상세보기
29. Bharath,Bhaskar; Cox,William D., Creating high-drive logic devices from standard gates with minimal use of custom masks.

    상세보기
30. Becker, Scott T.; Mali, Jim; Lambert, Carole, Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts.

    상세보기
31. Becker, Scott T.; Mali, Jim; Lambert, Carole, Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track.

    상세보기
32. Becker, Scott T.; Mali, Jim; Lambert, Carole, Cross-coupled transistor circuit defined on two gate electrode tracks.

    상세보기
33. Becker, Scott T.; Mali, Jim; Lambert, Carole, Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track.

    상세보기
34. Becker, Scott T.; Mali, Jim; Lambert, Carole, Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer.

    상세보기
35. Becker, Scott T.; Mali, Jim; Lambert, Carole, Cross-coupled transistor circuit including offset inner gate contacts.

    상세보기
36. Cox,William D., Customization of structured ASIC devices using pre-process extraction of routing information.

    상세보기
37. Kuiri, Tapio, Defect avoidance in an integrated circuit.

    상세보기
38. Vadi, Vasisht Mantra; Young, Steven P.; Ghia, Atul V.; Bekele, Adebabay M.; Menon, Suresh M., Differential clock tree in an integrated circuit.

    상세보기
39. Cox, William D., Distributed RAM in a logic array.

    상세보기
40. Sugisawa Junji (Santa Clara CA) Lalwani Dilip (Sunnyvale CA), Dynamic scan circuit and method for using the same.

    상세보기
41. Kornachuk, Stephen; Mali, Jim; Lambert, Carole; Becker, Scott T., Enforcement of semiconductor structure regularity for localized transistors and interconnect.

    상세보기
42. Kornachuk, Stephen; Mali, Jim; Lambert, Carole; Becker, Scott T., Enforcement of semiconductor structure regularity for localized transistors and interconnect.

    상세보기
43. Kornachuk, Stephen; Mali, Jim; Lambert, Carole; Becker, Scott T., Enforcement of semiconductor structure regularity for localized transistors and interconnect.

    상세보기
44. Beal Samuel W. ; Kaptonoglu Sinan ; Lien Jung-Cheun ; Shu William ; Chan King W. ; Plants William C., Enhanced field programmable gate array.

    상세보기
45. Beal,Samuel W.; Kaptonoglu,Sinan; Lien,Jung Cheun; Shu,William; Chan,King W.; Plants,William C., Enhanced field programmable gate array.

    상세보기
46. Klowak, Greg P.; McKnight-Macneil, Cameron; Tweddle, Howard; Mizan, Ahmad; Springett, Nigel, Fault tolerant design for large area nitride semiconductor devices.

    상세보기
47. Klowak, Gregory P.; McKnight-MacNeil, Cameron; Tweddle, Howard; Mizan, Ahmad; Springett, Nigel, Fault tolerant design for large area nitride semiconductor devices.

    상세보기
48. McGowan John E., Field programmable gate array with mask programmed analog function circuits.

    상세보기
49. John E. McGowan, Field programmable gate array with mask programmed input and output buffers.

    상세보기
50. McGowan John E., Field programmable gate array with mask programmed input and output buffers.

    상세보기
51. Becker, Scott T.; Smayling, Michael C.; Gandhi, Dhrumil; Mali, Jim; Lambert, Carole; Quandt, Jonathan R.; Fox, Daryl, Finfet transistor circuit.

    상세보기
52. Azmat, Raheel; Sengupta, Rwik; Park, Chulhong; Chun, Kwanyoung, Flip-flop layout architecture implementation for semiconductor device.

    상세보기
53. Bauer,Trevor J.; Young,Steven P., Formation of columnar application specific circuitry using a columnar programmable logic device.

    상세보기
54. Roberts, John; Mizan, Ahmad; Patterson, Girvan; Klowak, Greg, Gallium nitride power devices using island topography.

    상세보기
55. Roberts, John; Mizan, Ahmad; Patterson, Girvan; Klowak, Greg, Gallium nitride power devices using island topography.

    상세보기
56. Akram Salman ; Farnworth Warren M. ; Wood Alan G., High density flip chip memory arrays.

    상세보기
57. Akram, Salman; Farnworth, Warren M.; Wood, Alan G., High density flip chip memory arrays.

    상세보기
58. Guttag, Karl M.; Guttag, Alvin, Instructions controlling light modulating elements.

    상세보기
59. Smayling, Michael C.; Becker, Scott T., Integrated circuit cell library for multiple patterning.

    상세보기
60. Smayling, Michael C.; Becker, Scott T., Integrated circuit cell library for multiple patterning.

    상세보기
61. Smayling, Michael C.; Becker, Scott T., Integrated circuit cell library for multiple patterning.

    상세보기
62. Becker, Scott T.; Smayling, Michael C., Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length.

    상세보기
63. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channels.

    상세보기
64. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels.

    상세보기
65. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels.

    상세보기
66. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel.

    상세보기
67. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact.

    상세보기
68. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode.

    상세보기
69. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature.

    상세보기
70. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature.

    상세보기
71. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer.

    상세보기
72. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer.

    상세보기
73. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships.

    상세보기
74. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer.

    상세보기
75. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications.

    상세보기
76. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications.

    상세보기
77. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications.

    상세보기
78. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications.

    상세보기
79. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor.

    상세보기
80. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors.

    상세보기
81. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts.

    상세보기
82. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors.

    상세보기
83. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature.

    상세보기
84. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer.

    상세보기
85. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer.

    상세보기
86. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature.

    상세보기
87. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset relationships and electrical connection of cross-coupled transistors through same interconnect layer.

    상세보기
88. Becker, Scott T.; Smayling, Michael C., Integrated circuit including gate electrode conductive structures with different extension distances beyond contact.

    상세보기
89. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends.

    상세보기
90. Becker, Scott T.; Smayling, Michael C., Integrated circuit including linear gate electrode structures having different extension distances beyond contact.

    상세보기
91. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.

    상세보기
92. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.

    상세보기
93. Becker, Scott T.; Smayling, Michael C., Integrated circuit with gate electrode conductive structures having offset ends.

    상세보기
94. Becker, Scott T.; Smayling, Michael C., Integrated circuit with offset line end spacings in linear gate electrode level.

    상세보기
95. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit within semiconductor chip including cross-coupled transistor configuration.

    상세보기
96. Liu, Yow-Juang W.; O, Hugh; Cliff, Richard G., Integrated circuits with reduced standby power consumption.

    상세보기
97. Liu,Yow Juang W; O,Hugh Sungki; Cliff,Richard G, Integrated circuits with reduced standby power consumption.

    상세보기
98. Tai,Jan Sian; Ou,King, Interface for pin swap information.

    상세보기
99. Roberts, John; Mizan, Ahmad; Patterson, Girvan; Klowak, Greg, Island matrixed gallium nitride microwave and power switching transistors.

    상세보기
100. Cox, William D., Logic array devices having complex macro-cell architecture and methods facilitating use of same.

     상세보기
101. Cox, William D., Logic array devices having complex macro-cell architecture and methods facilitating use of same.

     상세보기
102. Guttag, Karl M., Mapping pixel values.

     상세보기
103. Park, Jonathan, Mask-programmable logic devices with programmable gate array sites.

     상세보기
104. Catalasan, Manolito M.; Rakshani, Vafa J.; Spittles, Edmund H.; Sippel, Tim; Unda, Richard, Memory cell for modification of revision identifier in an integrated circuit chip.

     상세보기
105. Aipperspach Anthony Gus ; Freiburger Peter Thomas, Method and apparatus for assembling array and datapath macros.

     상세보기
106. Iotov, Mihail; Pistorius, Erhard Joachim; Park, Jim; Karchmer, David, Method and apparatus for comparing programmable logic device configurations.

     상세보기
107. How, Dana; Srinivasan, Adi; Osann, Jr., Robert; Mukund, Shridhar, Method and apparatus for controlling and observing data in a logic block-based ASIC.

     상세보기
108. How Dana ; Srinivasan Adi ; Osann Robert ; Mukund Shridhar, Method and apparatus for controlling and observing data in a logic block-based asic.

     상세보기
109. Park, Jonathan, Method and apparatus for providing clock/buffer network in mask-programmable logic device.

     상세보기
110. Yuen, Joel T.; Maneparambil, Kailasnath S.; Singh, Puneet, Method and apparatus for scan design using a formal verification-based process.

     상세보기
111. Price, Richard, Method and apparatus for testing memory embedded in mask-programmable logic device.

     상세보기
112. Shiva P. Gowni ; Alpesh B. Patel, Method and apparatus for the automated generation of programmable interconnect matrices.

     상세보기
113. Raza S. Babar, Method and apparatus to generate mask programmable device.

     상세보기
114. Raza S. Babar, Method and apparatus to generate mask programmable device.

     상세보기
115. Raza S. Babar, Method and apparatus to generate mask programmable device.

     상세보기
116. Tain, Alex; Tosaya, Eric, Method for automatically routing connections between top side conductors and bottom side conductors of an integrated circuit package.

     상세보기
117. Tain,Alex; Tosaya,Eric, Method for automatically routing connections between top side conductors and bottom side conductors of an integrated circuit package.

     상세보기
118. Catalasan,Manolito M; Rakshani,Vafa J; Spittles,Edmund H; Sippel,Tim; Unda,Richard, Method for manufacturing a memory cell for modification of revision identifier in an integrated circuit chip.

     상세보기
119. Perry, Steven; Nixon, Gregor; Kong, Larry; Scott, Alasdair; Hall, Andrew; Wang, Lingli; Dettmar, Chris; Park, Jonathan; Price, Richard, Method for programming a mask-programmable logic device and device so programmed.

     상세보기
120. Perry,Steven; Nixon,Gregor; Kong,Larry; Scott,Alasdair; Hall,Andrew; Wang,Lingli; Dettmar,Chris; Park,Jonathan; Price,Richard, Method for programming a mask-programmable logic device and device so programmed.

     상세보기
121. Park, Jonathan; Chen, Eugen; Saito, Richard; Wright, Adam; Ratchev, Evgueni, Method of creating a mask-programmed logic device from a pre-existing circuit design.

     상세보기
122. Baxter Glenn A., Method to back annotate programmable logic device design files based on timing information of a target technology.

     상세보기
123. Phoon, Hee Kong; Chua, Kar Keng, Methods and apparatus for programmably powering down structured application-specific integrated circuits.

     상세보기
124. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell boundary encroachment and layouts implementing the Same.

     상세보기
125. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell boundary encroachment and layouts implementing the same.

     상세보기
126. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell boundary encroachment and semiconductor devices implementing the same.

     상세보기
127. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.

     상세보기
128. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.

     상세보기
129. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.

     상세보기
130. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.

     상세보기
131. Reed, Brian; Smayling, Michael C.; Becker, Scott T., Methods for controlling microloading variation in semiconductor wafer layout and fabrication.

     상세보기
132. Becker, Scott T.; Smayling, Michael C., Methods for designing semiconductor device with dynamic array section.

     상세보기
133. Smayling, Michael C.; Becker, Scott T., Methods for linewidth modification and apparatus implementing the same.

     상세보기
134. Smayling, Michael C.; Becker, Scott T., Methods for linewidth modification and apparatus implementing the same.

     상세보기
135. Fox, Daryl; Becker, Scott T., Methods for multi-wire routing and apparatus implementing same.

     상세보기
136. Fox, Daryl; Becker, Scott T., Methods for multi-wire routing and apparatus implementing same.

     상세보기
137. Fox, Daryl; Becker, Scott T., Methods for multi-wire routing and apparatus implementing same.

     상세보기
138. Akram, Salman; Farnworth, Warren M.; Wood, Alan G., Methods of a high density flip chip memory arrays.

     상세보기
139. Smayling, Michael C.; Becker, Scott T., Methods, structures, and designs for self-aligning local interconnects used in integrated circuits.

     상세보기
140. Smayling, Michael C.; Becker, Scott T., Methods, structures, and designs for self-aligning local interconnects used in integrated circuits.

     상세보기
141. Smayling, Michael C.; Becker, Scott T., Methods, structures, and designs for self-aligning local interconnects used in integrated circuits.

     상세보기
142. Smayling, Michael C.; Becker, Scott T., Methods, structures, and designs for self-aligning local interconnects used in integrated circuits.

     상세보기
143. Becker, Scott T., Oversized contacts and vias in layout defined by linearly constrained topology.

     상세보기
144. Becker, Scott T., Oversized contacts and vias in layout defined by linearly constrained topology.

     상세보기
145. Becker, Scott T., Oversized contacts and vias in layout defined by linearly constrained topology.

     상세보기
146. Bassett,Robert W.; Christensen,Garrett S; Combs,Michael L.; Farnsworth,L. Owen; Gillis,Pamela S., Parametric testing for high pin count ASIC.

     상세보기
147. Chan Andrew K. ; Birkner John M. ; Chua Hua-Thye, Programmable application specific integrated circuit and logic cell.

     상세보기
148. Chan Andrew K. (Palo Alto CA) Birkner John M. (Portola Valley CA) Chua Hua-Thye (Los Alto Hills CA), Programmable application specific integrated circuit and logic cell therefor.

     상세보기
149. Chan Andrew K. (Palo Alto CA) Birkner John M. (Woodside CA) Chua Hua T. (Los Altos Hills CA), Programmable application specific integrated circuit and logic cell therefor.

     상세보기
150. Chan Andrew K. ; Birkner John M. ; Chua Hua-Thye, Programmable application specific integrated circuit and logic cell therefor.

     상세보기
151. Chan Andrew K. ; Birkner John M. ; Chua Hua-Thye, Programmable application specific integrated circuit and logic cell therefor.

     상세보기
152. Gould Scott Whitney ; Keyser ; III Frank Ray ; Larsen Wendell Ray ; Worth Brian Allen, Programmable array interconnect latch.

     상세보기
153. Pileggi, Larry; Schmit, Herman, Programmable gate array based on configurable metal interconnect vias.

     상세보기
154. Catalasan, Manolito M.; Rakshani, Vafa J.; Spittles, Edmund H.; Sippel, Tim; Unda, Richard, Programmable memory cell in an integrated circuit chip.

     상세보기
155. Park, Jonathan; Kok, Yit Ping; Lim, Soon Chieh; Liew, Yin Hao; Chek, Wai Leng, Programmable via modeling.

     상세보기
156. Barbier, Jean; LePape, Olivier; Reblewski, Frederic, Reconfigurable integrated circuit with integrated debugging facilities and scalable programmable interconnect.

     상세보기
157. Reblewski Frederic,FRX ; Lepape Olivier,FRX, Reconfigurable integrated circuit with integrated debugging facilities for use in an emulation system.

     상세보기
158. Guttag, Karl M., Recursive feedback control of light modulating elements.

     상세보기
159. Smayling, Michael C.; Fox, Daryl; Quandt, Jonathan R.; Becker, Scott T., Scalable meta-data objects.

     상세보기
160. Smayling, Michael C.; Fox, Daryl; Quandt, Jonathan R.; Becker, Scott T., Scalable meta-data objects.

     상세보기
161. McCarthy Daniel M. ; Hollis Paul W. ; Yu Ruey J. ; Eisele Renny L., Scan based path delay testing of integrated circuits containing embedded memory elements.

     상세보기
162. Chou, Anthony I.; Dunn, James S.; Dufrene, Brian M.; Lumbra, Christopher H.; Narasimha, Shreesh; Putnam, Christopher S.; Rainey, BethAnn; Schnabel, Christopher M., Selectable device options for characterizing semiconductor devices.

     상세보기
163. Becker, Scott T.; Smayling, Michael C., Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures.

     상세보기
164. Becker, Scott T.; Smayling, Michael C., Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid.

     상세보기
165. Becker, Scott T.; Smayling, Michael C., Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid.

     상세보기
166. Kornachuk, Stephen; Mali, James; Lambert, Carole; Becker, Scott T.; Reed, Brian, Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires.

     상세보기
167. Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods.

     상세보기
168. Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods.

     상세보기
169. Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods.

     상세보기
170. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including integrated circuit defined within dynamic array section.

     상세보기
171. Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same.

     상세보기
172. Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same.

     상세보기
173. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same.

     상세보기
174. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same.

     상세보기
175. Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures.

     상세보기
176. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same.

     상세보기
177. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including region having rectangular-shaped gate structures and first metal structures.

     상세보기
178. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures.

     상세보기
179. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods.

     상세보기
180. Bose, Pradip; Kursun, Eren; Rivers, Jude A.; Zyuban, Victor, Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip.

     상세보기
181. Bose, Pradip; Kursun, Eren; Rivers, Jude A.; Zyuban, Victor, Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip.

     상세보기
182. Becker, Scott T.; Smayling, Michael C., Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos.

     상세보기
183. Corbett Tim J. ; Scholer Raymond P. ; Gonzalez Fernando, Semiconductor reliability test chip.

     상세보기
184. Corbett Tim J. ; Scholer Raymond P. ; Gonzalez Fernando, Semiconductor reliability test chip.

     상세보기
185. Corbett Tim J. ; Scholer Raymond P. ; Gonzalez Fernando, Semiconductor reliability test chip.

     상세보기
186. Corbett, Tim J.; Scholer, Raymond P.; Gonzalez, Fernando, Semiconductor reliability test chip.

     상세보기
187. Corbett, Tim J.; Scholer, Raymond P.; Gonzalez, Fernando, Semiconductor reliability test chip.

     상세보기
188. Smayling, Michael C., Super-self-aligned contacts and method for making the same.

     상세보기
189. Smayling, Michael C., Super-self-aligned contacts and method for making the same.

     상세보기
190. Smayling, Michael C., Super-self-aligned contacts and method for making the same.

     상세보기
191. Smayling, Michael C., Super-self-aligned contacts and method for making the same.

     상세보기
192. Baxter Glenn A., System and method for generating memory initialization logic in a target device with memory initialization bits from a programmable logic device.

     상세보기
193. Godiwala Nitin Dhiroobhai ; Ebert Andrew Myer ; Pawlowski Chester Walenty, Test methodology for exceeding tester pin count for an asic device.

     상세보기
194. Scott,Alasdair; Nixon,Gregor, Timing analysis for programmable logic.

     상세보기
195. Moran,Timothy G.; Dybsetter,Gerald L., Use of a third state applied to a digital input terminal of a circuit to initiate non-standard operational modes of the circuit.

     상세보기
196. Guttag, Karl M., Variable storage of bits on a backplane.

     상세보기
197. Buehler, Markus T.; Gangwar, Ankit; Koehl, Juergen; Mishra, Arun K., Via structure to improve routing of wires within an integrated circuit.

     상세보기
더보기