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Programmable array logic self-checking system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/28
출원번호 US-0306955 (1989-02-06)
발명자 / 주소
  • Dabbish Ezzat A. (Buffalo Grove IL) Puhl Larry C. (Sleepy Hollow IL) Brendle William L. (Carol Stream IL)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 66  인용 특허 : 0

초록

A self checking electronically erasable programmable array logic (EEPAL) that comprises an input receiver, a programmable array, an error detection code storage array, an error detection circuitry, and error signalling circuitry is disclosed. The self checking EEPAL verifies the storage integrity of

대표청구항

A self checking electronic erasable programmable array logic (EEPAL) comprising: input means for receiving an algorithm, a predetermined error detection code and data; programmable array means coupled to the input means for storing and executing the algorithm; error detection code storage means coup

이 특허를 인용한 특허 (66)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  16. Whetsel,Lee Doyle, Circuit with expected data memory coupled to serial input lead.
  17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  18. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  19. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  20. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  21. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  22. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  23. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  24. Abramovici Miron ; Stroud Charles E., Fault tolerant operation of field programmable gate arrays.
  25. Abramovici, Miron; Emmert, John M.; Stroud, Charles E., Fault tolerant operation of field programmable gate arrays.
  26. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  27. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  28. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  29. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  30. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  31. Whetsel, Lee D., Hierarchical linking module connection to access ports of embedded cores.
  32. Whetsel,Lee Doyle, IC with protocol selection memory coupled to serial scan path.
  33. Whetsel, Lee D., IC with shared scan cells selectively connected in scan path.
  34. Smith, David; Marsh, Andrew, Loading secure code into a memory.
  35. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  36. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  37. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  38. Abramovici Miron ; Stroud Charles Eugene ; Wijesuriya Sajitha S., Method and apparatus for testing field programmable gate arrays.
  39. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  40. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  41. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  42. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  43. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  44. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  45. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  46. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  47. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  48. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  49. Stroud Charles E. ; Abramovici Miron, Method for testing field programmable gate arrays.
  50. Stroud Charles E. ; Abramovici Miron, Method for testing field programmable gate arrays.
  51. Abramovici Miron ; Lee Eric Seng-Kar ; Stroud Charles Eugene, Method of testing and diagnosing field programmable gate arrays.
  52. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  53. Green,David J.; Pak,Sungyong, Methodology for JEDEC file repair through compression field techniques.
  54. Abramovici, Miron; Stroud, Charles E.; Emmert, John M., On-line fault tolerant operation via incremental reconfiguration of field programmable gate arrays.
  55. Whetsel, Lee D., Position independent testing of circuits.
  56. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  57. Von Wendorff, Christophorus W., Programmable unit.
  58. Whetsel, Lee D., Scan circuit low power adapter with counter.
  59. Whetsel,Lee Doyle, Scanning a protocol signal into an IC for performing a circuit operation.
  60. Whetsel,Lee D.; Haroun,Baher S.; Lasher,Brian J.; Kinra,Anjali, Selecting different 1149.1 TAP domains from update-IR state.
  61. Barry Robert L. ; Chickanosky John D. ; Oakland Steven F. ; Ouellette Michael R., Serial input shift register built-in self test circuit for embedded circuits.
  62. Master,Paul L.; Watson,John, Storage and delivery of device features.
  63. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  64. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  65. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  66. Green,David J.; Pak,Sungyong; Nan,Fangyuan, Techniques for JEDEC file information integrity and preservation of device programming specifications.
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