[특허]Distributed data driven process

[미국특허] Distributed data driven process 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-013/00 G06F-015/16
출원번호	US-0538349 (1990-06-14)
발명자 / 주소	Pian Chao-Kuang (Anaheim CA) Nguyen Minh-Tram D. (Anaheim CA) Posch Theodore E. (Fullerton CA) Juhre Jeffrey E. (Arlington Heights IL)
출원인 / 주소	Hughes Aircraft Company (Los Angeles CA 02)
인용정보	피인용 횟수 : 43 인용 특허 : 0

초록 ▼

A data driven method for coordinating the processing of arithmetic tasks in a multiple computer system having a multiplicity of arithmetic processors by determining whether an arithmetic task is in a blocked condition or is in an execution ready condition. A source distributed processor stores data in a local memory for processing by a local processor and then transfers the processed data to a global memory for buffering in preparation for subsequent processing by a destination distributed processor. The source distributed processor generates a produce message to a destination distributed processor to indicate that the data to be transferred is available in a buffer in the global memory. The destination distributed processor loads the data to be transferred from the buffer in the global memory and then generates a consume message to the source distributed processor to indicate that the data has been transferred from the global memory and the buffer in the global memory is now available.

대표청구항 ▼

A data driven method for coordinating the processing of arithmetic tasks in a multiple computer system having a plurality of arithmetic processors by determining whether an arithmetic task is in a blocked condition or is in an execution ready condition, said method comprising the following steps: receiving data comprising a first arithmetic task including input data elements in a first arithmetic processor; transferring said data from said first arithmetic processor to global memory; generating a produce message in said first arithmetic processor; transferring said produce message to a second arithmetic processor; determining availability of local memory in said second arithmetic processor in response to said produce message; transferring said data from said global memory to the local memory in said second arithmetic processor in response to finding sufficient local memory available; generating a consume message in said second arithmetic processor; transferring said consume message to said first arithmetic processor; comparing the number of input data elements present in said data with a predetermined necessary number to perform said first arithmetic task; comparing the amount of local memory available with the necessary amount required to store the result after performing said first arithmetic task; determining whether said first arithmetic task is in an execution ready condition or is in a blocked condition; and executing said first arithmetic task when it is in an execution ready condition.

이 특허를 인용한 특허 (43) 인용/피인용 타임라인 분석

Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
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Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
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Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
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Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
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Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
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Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
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Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
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Heidari Bateni,Ghobad; Sambhwani,Sharad D., Data flow control for adaptive integrated circuitry.
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Furtek, Frederick Curtis; Master, Paul L., External memory controller.
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Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
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Hendel, Ariel; Gajjar, Yatin; Lin, May; Pun, Rahoul; Wong, Michael, Method and apparatus for efficient interrupt event notification for a scalable input/output device.
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Master, Paul L., Method and system for achieving individualized protected space in an operating system.
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Master, Paul L., Method and system for creating and programming an adaptive computing engine.
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Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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Scheuermann, W. James, Method and system for reconfigurable channel coding.
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Scheuermann, W. James, Method and system for reconfigurable channel coding.
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Scheuermann, W. James, Method and system for reconfigurable channel coding.
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Scheuermann, W. James, Method and system for reconfigurable channel coding.
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Toub, Stephen H.; Yildiz, Huseyin S.; Hoag, Joseph E.; Duffy, John J.; Shih, Danny, Plug-in task scheduler.
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Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
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Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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[미국특허] Distributed data driven process 원문보기

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