초록 ▼

For the employment of an FEC method in systems of a variety of types, the serial binary data stream to be transmitted is supplied to a means for rate matching and for serial-to-parallel conversion wherein, first, the data rate is increased to the transmission rate upon formation of free locations fo

For the employment of an FEC method in systems of a variety of types, the serial binary data stream to be transmitted is supplied to a means for rate matching and for serial-to-parallel conversion wherein, first, the data rate is increased to the transmission rate upon formation of free locations for the acceptance of redundancy bits and, second, a corresponding plurality of parallel data streams are generated from the serial data stream, respectively one half of said parallel data streams forming the I-channel and the other half forming the Q-channel. The redundancy locations lie in the least significant bits of the I-channel and Q-channel. The more significant bits of the I-channel and the Q-channel directly control the appertaining inputs of a quadrature modulator, whereas the least significant bit is supplied to the appertaining input via a respective multiplexer. In addition, the least significant bit of the I-channel and the Q-channel is respectively supplied to a coder, each of these coders considering a defined plurality of incoming bits; and generating one or more redundancy bits therefrom in accord with the coding rule of a specific underlaid code. These redundancy bits are inserted with the assistance of the multiplexers at locations in the I-channel and Q-channel, that are provided for this purpose.

대표청구항 ▼

A method for redundancy-saving, error-correcting coding in digital radial link systems having multi-level modulation, using forward error correction, comprising the steps of: supplying the serial binary data stream to be transmitted to a means for rate matching and serial-to-parallel conversion, in

A method for redundancy-saving, error-correcting coding in digital radial link systems having multi-level modulation, using forward error correction, comprising the steps of: supplying the serial binary data stream to be transmitted to a means for rate matching and serial-to-parallel conversion, in which first, the data rate is increased to the transmission rate and three locations are formed for the acceptance of redundancy bits and, second, a corresponding plurality of parallel data streams is generated from the serial data stream, with one half of these parallel data streams forming the I-channel and, the other half forming the Q-channel; supplying the least significant bit of the I-channel and the least significant bit of the Q-channel, in which the redundancy locations lie, to the two inputs of a multiplexer, first directly and, secondly, via a coder, the output side of said multiplexer being connected to a quadrature modulator, with the more significant bits of the I-channel and Q-channel directly controlling corresponding inputs of said quadrature modulator; said coders each receiving inputs from said means for rate matching and serial-to-parallel conversion in the form of a sequence consisting of a defined plurality of k incoming bits to generate one or more redundancy bits therefrom in accord with the coding rule of an underlaid code, said redundancy bits being inserted with the assistance of said multiplexer at locations in the I-channel and Q-channel; and correcting transmission errors in a decoder means.