$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

High performance interconnect system for an integrated circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • B44C-001/22
  • C03C-015/00
  • C23F-001/02
출원번호 US-0610962 (1990-11-08)
발명자 / 주소
  • Thomas Michael E. (Cupertino CA) Chinn Jeffrey D. (Foster City CA)
출원인 / 주소
  • Fairchild Camera and Instrument Corp. (Mountain View CA 02)
인용정보 피인용 횟수 : 124  인용 특허 : 0

초록

A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is

대표청구항

A semiconductor integrated circuit device including an interconnect structure for electrically connecting regions in a semiconductor substrate having contact areas disposed in a predetermined spaced relation, said interconnect structure comprising: a first level of interconnects disposed above said

이 특허를 인용한 특허 (124)

  1. Chen, Chien-Hua; Chen, Zhizhang; Meyer, Neal W., 3D interconnect with protruding contacts.
  2. Chen,Chien Hua; Chen,Zhizhang; Meyer,Neal W., 3D interconnect with protruding contacts.
  3. Geffken,Robert M.; Motsiff,William T., Adjustable self-aligned air gap dielectric for low capacitance wiring.
  4. Geffken,Robert M.; Motsiff,William T., Adjustable self-aligned air gap dielectric for low capacitance wiring.
  5. Gardner Mark I. ; Kadosh Daniel ; Duane Michael P., Air gap spacer formation for high performance MOSFETs.
  6. Farrar Paul A., Aluminum based alloy bridge structure and method of forming same.
  7. Farrar, Paul A., Aluminum based alloy bridge structure and method of forming same.
  8. Ashtiani, Kaihan A.; Biberger, Maximilian A.; Klawuhn, Erich R.; Lai, Kwok Fai; Levy, Karl B.; Rymer, J. Patrick, Apparatus and method for depositing superior Ta (N) copper thin films for barrier and seed applications in semiconductor processing.
  9. Ashtiani, Kaihan A.; Biberger, Maximilian A.; Klawuhn, Erich R.; Lai, Kwok Fai; Levy, Karl B.; Rymer, J. Patrick, Apparatus and method for depositing superior Ta(N)/copper thin films for barrier and seed applications in semiconductor processing.
  10. Nowak Edward D. ; Bothra Subhas, Apparatus for automated pillar layout.
  11. Nowak Edward D. ; Bothra Subhas, Apparatus for automated pillar layout and method for implementing same.
  12. Chow, Lap-Wai; Hsu, Tsung-Yuan; Hyman, Daniel J.; Loo, Robert Y.; Ouyang, Paul; Schaffner, James H.; Schmitz, Adele; Schwartz, Robert N., CMOS-compatible MEM switches and method of making.
  13. Baukus James P. ; Chow Lap-Wai ; Clark ; Jr. William M., Camouflaged circuit structure with step implants.
  14. Li, Delin, Circuit board and a method for making the same.
  15. Claude Louis Bertin ; Gordon Arthur Kelley ; Dennis Arthur Schmidt ; William Robert Tonti ; Jerzy Maria Zalesinski, Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality.
  16. Chow, Lap-Wai; Clark, Jr., William M.; Harbison, Gavin J.; Baukus, James P., Conductive channel pseudo block process and circuit to inhibit reverse engineering.
  17. Chow, Lap-Wai; Clark, Jr., William M.; Harbison, Gavin J.; Baukus, James P., Conductive channel pseudo block process and circuit to inhibit reverse engineering.
  18. Chow,Lap Wai; Clark, Jr.,William M.; Harbison,Gavin J.; Baukus,James P., Conductive channel pseudo block process and circuit to inhibit reverse engineering.
  19. Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  20. Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  21. Chow, Lap Wai; Clark, Jr., William M.; Baukus, James P., Covert transformation of transistor properties as a circuit protection method.
  22. Chow,Lap Wai; Clark, Jr.,William M.; Baukus,James P., Covert transformation of transistor properties as a circuit protection method.
  23. H. Jim Fulford, Jr. ; Robert Dawson ; Fred N. Hause ; Basab Bandyopadhyay ; Mark W. Michael ; William S. Brennan, Dielectric having an air gap formed between closely spaced interconnect lines.
  24. Baukus James P. ; Chow Lap Wai ; Clark ; Jr. William M., Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering.
  25. Baukus James P. ; Chow Lap Wai ; Clark ; Jr. William M., Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering.
  26. Baukus James P. ; Chow Lap Wai ; Clark ; Jr. William M., Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering.
  27. Hause Fred N. ; Bandyopadhyay Basab ; Dawson Robert ; Fulford ; Jr. H. Jim ; Michael Mark W. ; Brennan William S., Dissolvable dielectric method.
  28. Hause Fred N. ; Bandyopadhyay Basab ; Dawson Robert ; Fulford ; Jr. H. Jim ; Michael Mark W. ; Brennan William S., Dissolvable dielectric method and structure.
  29. Filippi, Ronald G.; Fitzsimmons, John A.; Kolvenbach, Kevin; Wang, Ping-Chuan, Electromigration immune through-substrate vias.
  30. Bhattacharyya Arup ; Leidy Robert K., Embedded power and ground plane structure.
  31. DeBoer, Scott J.; Al-Shareef, Husam N., Fabrication of semiconductor devices with transition metal boride films as diffusion barriers.
  32. DeBoer, Scott J.; Al-Shareef, Husam N., Fabrication of semiconductor devices with transition metal boride films as diffusion barriers.
  33. DeBoer, Scott J.; Al-Shareef, Husam N., Fabrication of semiconductor devices with transition metal boride films as diffusion barriers.
  34. Hall Bart,CAX ; Grodski Julius J.,CAX, Force generation device for simulation of shoulder-supported rocket launching.
  35. Mina, Essam; Wang, Guoan; Woods, Jr., Wayne H., High performance on-chip vertical coaxial cable, method of manufacture and design structure.
  36. Mina, Essam; Wang, Guoan; Woods, Jr., Wayne Harvey, High performance on-chip vertical coaxial cable, method of manufacture and design structure.
  37. Jeng Shin-Puu ; Chang Mi-Chang, Highly thermally conductive interconnect structure for intergrated circuits.
  38. Clark, Jr., William M.; Baukus, James P.; Chow, Lap-Wai, Implanted hidden interconnections in a semiconductor device for preventing reverse engineering.
  39. Clark, Jr.,William M.; Baukus,James P.; Chow,Lap Wai, Implanted hidden interconnections in a semiconductor device for preventing reverse engineering.
  40. Smooha Yehuda, Integrated circuit conductors that avoid current crowding.
  41. Chow, Lap Wai; Clark, Jr., William M.; Baukus, James P.; Harbison, Gavin J., Integrated circuit modification using well implants.
  42. Chow, Lap-Wai; Clark, Jr., William M.; Baukus, James P; Harbison, Gavin J., Integrated circuit modification using well implants.
  43. Baukus James P. ; Clark ; Jr. William M. ; Chow Lap-Wai ; Kramer Allan R., Integrated circuit security system and method with implanted interconnections.
  44. Baukus, James P.; Chow, Lap-Wai; Clark, Jr., William M., Integrated circuit structure with programmable connector/isolator.
  45. Gardner Mark I. ; Spikes Thomas E. ; Paiz Robert, Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths.
  46. Chow, Lap-Wai; Clark, Jr., William M.; Baukus, James P., Integrated circuit with reverse engineering protection.
  47. Chow,Lap Wai; Clark, Jr.,William M.; Baukus,James P., Integrated circuit with reverse engineering protection.
  48. Manning,Monte, Integrated circuitry and a semiconductor processing method of forming a series of conductive lines.
  49. Manning,Monte, Integrated circuitry and a semiconductor processing method of forming a series of conductive lines.
  50. Manning, Monte, Integrated circuitry conductive lines.
  51. Chow,Lap Wai; Baukus,James P.; Clark, Jr.,William M., Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide.
  52. Chow, Lap-Wai; Baukus, James P.; Clark, Jr., William M., Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations.
  53. Brugge Hunter Barham (San Antonio TX), Integrated-circuit via formation using gradient photolithography.
  54. Yang, Chih-Chao; Horak, David V.; Nogami, Takeshi; Ponoth, Shom, Interconnect structure with a mushroom-shaped oxide capping layer and method for fabricating same.
  55. Kwon, Jinsu; Endo, Kimitaka; Moran, Sean P., Interconnection element with posts formed by plating.
  56. Hong Gary (Hsinchu TWX), Interconnection with self-aligned via plug.
  57. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Interlevel dielectric with air gaps to lessen capacitive coupling.
  58. Buynoski, Matthew S., Low dielectric metal silicide lined interconnection system.
  59. Buynoski Matthew S., Low dielectric semiconductor device with rigid, conductively lined interconnection system.
  60. Alfred Grill ; Christopher Vincent Jahnes ; Vishnubhai Vitthalbhai Patel, Method for fabricating a thermally stable diamond-like carbon film as an intralevel or interlevel dielectric in a semiconductor device and device made.
  61. Dornel, Erwan, Method for forming a floating gate in a recess of a shallow trench isolation (STI) region.
  62. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  63. Chiang Chien ; Fraser David B., Method for forming multileves interconnections for semiconductor fabrication.
  64. Bae Sang Man,KRX ; Baik Ki Ho,KRX, Method for forming resist patterns comprising two photoresist layers and an intermediate layer.
  65. Bae Sang Man,KRX ; Baik Ki Ho,KRX, Method for forming resist patterns having two photoresist layers and an intermediate layer.
  66. Sekiguchi Mitsuru,JPX, Method for making semiconductor device containing low carbon film for interconnect structures.
  67. Horak, David Vaclav; Koburger, III, Charles William; Mitchell, Peter H.; Nesbit, Larry Alan, Method for manufacturing a multi-level interconnect structure.
  68. Min, Heikyung; Kurihara, Steven; Spence, Robert, Method for reducing surface zener drift.
  69. Shih, Hui Shen, Method of etching a dielectric layer to form a contact hole and a via hole and damascene method.
  70. Kwon, Jinsu; Endo, Kimitaka; Moran, Sean, Method of fabricating an interconnection element having conductive posts.
  71. Gardner Mark I. ; Kadosh Daniel ; Duane Michael P., Method of forming air gap spacer for high performance MOSFETS'.
  72. Tuttle Mark E. (Boise ID), Method of forming battery terminal housing members and battery terminal housing member sheets.
  73. Livio Baldi IT, Method of forming high-stability metallic contacts in an integrated circuit with one or more metallized layers.
  74. Buynoski Matthew S., Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system.
  75. Buynoski Matthew S., Method of forming low dielectric tungsten lined interconnection system.
  76. Nien-Yu Tsai TW; Hong-Long Chang TW; Chun-Wei Chen TW; Ming-Li Kung TW, Method of forming tungsten interconnect and vias without tungsten loss during wet stripping of photoresist polymer.
  77. Taguchi Mitsuru,JPX ; Maeda Keiichi,JPX, Method of forming wirings.
  78. Taguchi Mitsuru,JPX ; Maeda Keiichi,JPX, Method of forming wirings.
  79. Lin Shih-Chi,TWX ; Chen Yen-Ming,TWX ; Chang Juin-Jie,TWX ; Huang Kuei-Wu,TWX, Method of manufacturing air gap in multilevel interconnection.
  80. Akram, Salman; Meikle, Scott G., Method of using tantalum-aluminum-nitrogen material as diffusion barrier and adhesion layer in semiconductor devices.
  81. Salman Akram ; Scott G. Meikle, Method of using tantalum-aluminum-nitrogen material as diffusion barrier and adhesion layer in semiconductor devices.
  82. Weling, Milind; Bothra, Subhas; Gabriel, Calvin Todd; Misheloff, Michael, Methods for forming co-axial interconnect lines in a CMOS process for high speed applications.
  83. Bothra Subhas ; Qian Ling Q., Methods for making semiconductor devices having air dielectric interconnect structures.
  84. Tuttle Mark E. (Boise ID), Methods of forming a button-type battery terminal housing member sheet and of forming button-type batteries.
  85. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  86. Manning Monte, Methods of forming conductive lines.
  87. Dawson Robert ; Michael Mark W. ; Brennan William S. ; Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Hause Fred N., Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnec.
  88. Dawson Robert ; Michael Mark W. ; Brennan William S. ; Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Hause Fred N., Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect.
  89. Makoto Sasaki JP, Multilevel interconnection structure having an air gap between interconnects.
  90. Sasaki Makoto,JPX, Multilevel interconnection structure having an air gap between interconnects.
  91. Baukus, James P.; Chow, Lap-Wai; Clark, Jr., William M., Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact.
  92. Baukus, James P.; Chow, Lap-Wai; Clark, Jr., William M., Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact.
  93. Baukus, James P.; Clark, Jr., William M.; Chow, Lap-Wai; Kramer, Allan R., Process for fabricating secure integrated circuit.
  94. Clark, Jr., William M.; Chow, Lap Wai; Harbison, Gavin; Ouyang, Paul, Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer.
  95. Clark, Jr., William M.; Chow, Lap Wai; Harbison, Gavin; Ouyang, Paul, Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer.
  96. Baukus, James P.; Chow, Lap-Wai; Clark, Jr., William M., Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same.
  97. Stephen L. Skala ; Subhas Bothra, Programmable integrated circuit structures and methods for making the same.
  98. Kloster,Grant; Wu,Chih I; Morrow,Xiaorong, Sealing porous dielectrics with silane coupling reagents.
  99. Baukus James P. ; Clark ; Jr. William M. ; Chow Lap-Wai ; Kramer Allan R., Secure integrated circuit.
  100. Sullivan Timothy D., Semiconductor chip structures with embedded thermal conductors.
  101. Sekiguchi, Mitsuru, Semiconductor device and method for fabricating the same.
  102. Tanahashi Toru,JPX, Semiconductor device having a reliable contact structure.
  103. Masamitsu Ikumo JP; Toshimi Kawahara JP; Norio Fukasawa JP; Kenichi Nagashige JP, Semiconductor device having improved electrical characteristics and method of producing the same.
  104. Liu, Yong; Zhang, Jiangyuan; Qian, Qiuxiao, Semiconductor die package including IC driver and bridge.
  105. Chow, Lap-Wai; Clark, Jr., William M.; Harbison, Gavin J.; Ou Yang, Paul, Symmetric non-intrusive and covert technique to render a transistor permanently non-operable.
  106. Chow,Lap Wai; Clark, Jr.,William M.; Harbison,Gavin J.; Yang,Paul Ou, Symmetric non-intrusive and covert technique to render a transistor permanently non-operable.
  107. Salman Akram ; Scott G. Meikle, Tantalum - aluminum - nitrogen material for semiconductor devices.
  108. Akram Salman ; Meikle Scott G., Tantalum-aluminum-nitrogen material for semiconductor devices.
  109. Akram Salman ; Meikle Scott G., Tantalum-aluminum-nitrogen material for semiconductor devices.
  110. Akram, Salman; Meikle, Scott G., Tantalum-aluminum-nitrogen material for semiconductor devices.
  111. Iyer, Ravi, Titanium boride gate electrode and interconnect.
  112. Iyer, Ravi, Titanium boride gate electrode and interconnect.
  113. Iyer Ravi, Titanium boride gate electrode and interconnect and methods regarding same.
  114. Iyer, Ravi, Titanium boride gate electrode and interconnect and methods regarding same.
  115. Iyer,Ravi, Titanium silicide boride gate electrode.
  116. Moslehi Mehrdad M., Ultra high-speed chip interconnect using free-space dielectrics.
  117. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.
  118. Tsai Jun-Lin,TWX ; Ho Yen-Shih,TWX, Uniform sidewall profile etch method for forming low contact leakage schottky diode contact.
  119. Chow, Lap-Wai; Clark, Jr., William M.; Harbison, Gavin J.; Baukus, James P., Use of silicide block process to camouflage a false transistor.
  120. Chow, Lap-Wai; Clark, Jr., William M.; Harbison, Gavin J.; Baukus, James P., Use of silicon block process step to camouflage a false transistor.
  121. Chow,Lap Wai; Clark, Jr.,William M.; Harbison,Gavin J.; Baukus,James P., Use of silicon block process step to camouflage a false transistor.
  122. Graham, Andrew B.; Yama, Gary; O'Brien, Gary, Wafer with spacer including horizontal member.
  123. Licata Thomas John ; Mandelman Jack Allan, Wire shape conferring reduced crosstalk and formation methods.
  124. Sim Jae Kwang,KRX ; Lee Sang Ho,KRX, Wiring structure of semiconductor memory device and formation method thereof.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로