이 특허를 인용한 특허 (50)

1. Tuan, Hsing Ti; Leung, Chung Wai, Dummy structures that protect circuit elements during polishing.

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2. Tuan, Hsing Ti; Leung, Chung Wai, Dummy structures that protect circuit elements during polishing.

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3. Chen Jian (San Jose CA) Tang Yuan (San Jose CA) Luning Scott (Menlo Park CA) Cagnina Salvatore F. (Los Altos CA), Flash EEPROM memory with reduced column leakage current.

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4. Haddad, Sameer, Flash memory array architecture and method of programming, erasing and reading thereof.

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5. Haddad, Sameer; Fastow, Richard, Flash memory array architecture having staggered metal lines.

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6. Chen Jian ; Fong Yupin, High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gat.

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7. Sung Kuo-Tung,TWX, High density programmable read-only memory employing double-wall spacers.

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8. Yamazaki,Shunpei, Light-emitting device and method of manufacturing same.

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9. Yamazaki,Shunpei, Light-emitting device and method of manufacturing the same.

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10. Richard Fastow, Low column leakage nor flash array-double cell implementation.

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11. Chang Shang-De (Fremont CA) Chang Jia-Hwang (Cupertino CA) Chow Edwin (Saratoga CA), Low voltage one transistor flash EEPROM cell using Fowler-Nordheim programming and erase.

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12. Chang Shang-De (Fremont CA) Chang Jia-Hwang (Cupertino CA) Chow Edwin (Saratoga CA), Low voltage one transistor flash EEPROM cell using Fowler-Nordheim programming and erase.

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13. Chang Shang-De (Fremont CA) Chang Jia-Hwang (Cupertino CA) Chow Edwin (Saratoga CA), Low voltage one transistor flash eeprom cell using fowler-nordheim programming and erase.

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14. Lee, Wook-Hyoung, Memory device and method of manufacturing the same.

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15. Jung,Sung Mun; Kim,Dong Oog, Method for fabricating a semiconductor device.

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16. Park Jin Won,KRX, Method for fabricating a semiconductor memory cell structure.

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17. Han,Chang Hun, Method for fabricating semiconductor device by forming trenches in different depths at a cellregion and a peripheral region for reducing self aligned source resistance at the cell region.

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18. Hsieh Chia-Ta,TWX ; Lin Chrong Jung,TWX ; Chen Shui-Hung,TWX ; Kuo Di-Son,TWX, Method for forming mirror image split gate flash memory devices by forming a central source line slot.

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19. Choi Yong-ju,KRX ; Choi Jeong-hyuk,KRX, Method for manufacturing nonvolatile memory device capable of preventing damage to side walls of stacked gate and active region.

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20. Wenge Yang ; John Jianshi Wang ; Hao Fang, Method for reducing the step height of shallow trench isolation structures.

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21. Hsieh Chia-Ta,TWX ; Lin Yai-Fen,TWX ; Sung Hung-Cheng,TWX ; Kuo Di-Son,TWX, Method for shrinking array dimensions of split gate flash memory device using multilayer etching to define cell and source line.

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22. Park Young-Keun,KRX, Method of fabricating flash memory cell.

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23. Ghneim Said N. ; Fulford ; Jr. H. Jim, Method of making non-volatile memory device having a floating gate with enhanced charge retention.

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24. Chen Jong,TWX ; Lin Chrong Jung,TWX, Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby.

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25. Fastow, Richard; Haddad, Sameer; Wang, Zhigang; Park, Sheung-Hee, Method of programming memory cells.

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26. Chen,Jian, Method of reading NAND memory to compensate for coupling between storage elements.

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27. Cho Kyung-rae,KRX ; Kim Keon-soo,KRX ; Kim Jin-woo,KRX, Methods of forming memory devices having protected gate electrodes.

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28. Ghneim Said N. ; Fulford ; Jr. H. Jim, Non-volatile memory device having a floating gate with enhanced charge retention.

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29. Jeong-hyuk Choi KR; Yong-ju Choi KR; Kyung-joong Joo KR; Keon-soo Kim KR, Nonvolatile memory device having bulk bias contact structure in cell array region.

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30. Hsing Ti Tuan ; Li-Chun Li ; Chung Wai Leung ; Thomas Tong-Long Chang, Nonvolatile memory structures and fabrication methods.

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31. Leung, Chung Wai; Hsiao, Chia-Shun; Chan, Vei-Han, Nonvolatile memory structures and fabrication methods.

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32. Leung, Chung Wai; Hsiao, Chia-Shun; Chan, Vei-Han, Nonvolatile memory structures and fabrication methods.

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33. Leung, Chung Wai; Hsiao, Chia-Shun; Chan, Vei-Han, Nonvolatile memory structures and fabrication methods.

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34. Tuan, Hsing Ti; Li, Li-Chun, Nonvolatile memory structures and fabrication methods.

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35. Tuan, Hsing Ti; Li, Li-Chun, Nonvolatile memory structures and fabrication methods.

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36. Tuan, Hsing Ti; Li, Li-Chun; Chang, Thomas Tong-Long, Nonvolatile memory structures and fabrication methods.

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37. Tripsas Nicholas Harris ; Ramsbey Mark T., Process for fabricating a common source region in memory devices.

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38. Hall Mark D. ; Ferguson Gregory Steven ; Mitchell Joel Patrick ; Suryanata Johanes P. D., Process for forming a semiconductor device.

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39. Zhou Mei Sheng,SGX ; Loong Sheau-Tan,SGX ; Tan Koon Lay Denise,SGX ; Li Jian Xun,SGX ; Chiu Wing Hong,SGX ; Tang Kok Hiang Stephanie,SGX, Process improvements in self-aligned polysilicon MOSFET technology using silicon oxynitride.

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40. Lin Ruei-Ling,TWX ; Hsu Ching-Hsiang,TWX ; Liang Mong-Song,TWX, Self-aligned source process.

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41. Ratnam Perumal, Semiconductor device having reduced source leakage during source erase.

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42. Shimoji Noriyuki,JPX, Semiconductor memory device and method of manufacturing thereof.

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43. Wang Hsingya Arthur ; Chen Jian ; Steffan Paul J., Simplified process for fabricating flash eeprom cells.

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44. Hsieh, Chia-Ta; Liu, Yai-Fen; Sung, Hung-Cheng; Kuo, Di-Son, Split gate flash memory device with shrunken cell and source line array dimensions.

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45. Hsieh Chia-Ta,TWX ; Lin Chrong Jung,TWX ; Chen Shui-Hung,TWX ; Kuo Di-Son,TWX, Split gate flash memory device with source line.

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46. Ratnam Perumal, Technique to improve the source leakage of flash EPROM cells during source erase.

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47. Liu Yowjuang W. ; Sun Yu, Three-dimensional complementary field effect transistor process and structures.

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48. Liu Yowjuang W. ; Haddad Sameer S., Three-dimensional non-volatile memory.

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49. Liu Yowjuang W. ; Haddad Sameer S., Three-dimensional non-volatile memory.

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50. Hsieh Chia-Ta,TWX ; Kuo Di-Son,TWX ; Lin Yai-Fen,TWX ; Sung Hung-cheng,TWX, Two mask method for reducing field oxide encroachment in memory arrays.

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