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| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0665103 (1991-03-06) |
| 발명자 / 주소 |
|
| 출원인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 277 인용 특허 : 0 |
A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND
A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
An application specific integrated circuit comprising: a plurality of generally parallel first conductors; a plurality of generally parallel second conductors including one or more voltage supply conductors, said first and second conductors crossing in a first crossover region and being generally in
An application specific integrated circuit comprising: a plurality of generally parallel first conductors; a plurality of generally parallel second conductors including one or more voltage supply conductors, said first and second conductors crossing in a first crossover region and being generally insulated from one another in said first crossover region; a plurality of first programmable links disposed in said first crossover region, preselected crossings of said first conductors and said second conductors having disposed therebetween respective first programmable links; a logic cell having inputs and outputs comprising a plurality of generally parallel third conductors including one or more cell input conductors and one or more cell output conductors, said second and third conductors crossing in a second crossover region and being generally insulated from one another in said second crossover region; and a plurality of second programmable links disposed in said second crossover region, preselected crossings of said second conductors and said third conductors having disposed therebetween respective second programmable links; wherein programmable links are disposed between crossings of said voltage supply conductors and said cell input conductors; and programmable links are absent between crossings of said voltage supply conductors and said cell output conductors.
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