이 특허를 인용한 특허 (214)

1. Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Adder-rounder circuitry for specialized processing block in programmable logic device.

   상세보기
2. Langhammer, Martin, Angular range reduction in an integrated circuit device.

   상세보기
3. Wirtz, II, Frank C., Apparatus and method for preinitializing logic function.

   상세보기
4. Sung Chiakang (Milpitas CA) Chang Wanli (Saratoga CA) Huang Joseph (San Jose CA), Apparatus for serial reading and writing of random access memory arrays.

   상세보기
5. Sung Chiakang ; Chang Wanli ; Huang Joseph, Apparatus for serial reading and writing of random access memory arrays.

   상세보기
6. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.

   상세보기
7. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.

   상세보기
8. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.

   상세보기
9. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.

   상세보기
10. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.

    상세보기
11. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.

    상세보기
12. Langhammer,Martin; Prasad,Nitin, Circuitry for arithmetically accumulating a succession of arithmetic values.

    상세보기
13. Langhammer, Martin, Combined adder and pre-adder for high-radix multiplier circuit.

    상세보기
14. Langhammer, Martin, Combined floating point adder and subtractor.

    상세보기
15. Mauer, Volker, Combined interpolation and decimation filter for programmable logic device.

    상세보기
16. Langhammer, Martin, Computing floating-point polynomials in an integrated circuit device.

    상세보기
17. Langhammer, Martin; Pasca, Bogdan, Computing floating-point polynomials in an integrated circuit device.

    상세보기
18. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.

    상세보기
19. Langhammer, Martin, Configuring a programmable integrated circuit device to perform matrix multiplication.

    상세보기
20. Langhammer, Martin, Configuring floating point operations in a programmable device.

    상세보기
21. Langhammer, Martin, Configuring floating point operations in a programmable logic device.

    상세보기
22. Manohararajah, Valavan; Lewis, David, Configuring programmable integrated circuit device resources as processing elements.

    상세보기
23. Francis B. Heile, Content addressable memory encoded outputs.

    상세보기
24. Leung, Wai-Bor; Lui, Henry Y., DSP block for implementing large multiplier on a programmable integrated circuit device.

    상세보기
25. Langhammer, Martin, DSP processor architecture with write datapath word conditioning and analysis.

    상세보기
26. Langhammer, Martin, DSP processor architecture with write datapath word conditioning and analysis.

    상세보기
27. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

    상세보기
28. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

    상세보기
29. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

    상세보기
30. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.

    상세보기
31. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.

    상세보기
32. Vorbach, Martin, Data processing system.

    상세보기
33. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.

    상세보기
34. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.

    상세보기
35. Langhammer, Martin; Starr, Gregory; Hwang, Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.

    상세보기
36. Langhammer, Martin; Starr, Gregory; Hwang, Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.

    상세보기
37. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.

    상세보기
38. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.

    상세보기
39. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.

    상세보기
40. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.

    상세보기
41. Demirsoy, Suleyman; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.

    상세보기
42. Langhammer, Martin, Digital signal processing circuitry with redundancy and ability to support larger multipliers.

    상세보기
43. Langhammer, Martin; Lin, Yi-Wen; Streicher, Keone, Digital signal processing circuitry with redundancy and bidirectional data paths.

    상세보기
44. Langhammer, Martin, Discrete Fourier Transform in an integrated circuit device.

    상세보기
45. Langhammer, Martin, Double-clocked specialized processing block in an integrated circuit device.

    상세보기
46. Srinivas T. Reddy ; Christopher F. Lane ; Manuel Mejia ; Richard G. Cliff ; Kerry Veenstra, Dual port programmable logic device variable depth and width memory array.

    상세보기
47. Reddy Srinivas T. ; Lane Christopher F. ; Mejia Manuel ; Cliff Richard G. ; Veenstra Kerry, Dual-port programmable logic device variable depth and width memory array.

    상세보기
48. Vorbach Martin Andreas,DEX ; Munch Robert Markus,DEX, Dynamically reconfigurable data processing system.

    상세보기
49. Steele Randy Charles ; Chinnow ; Jr. Duane H., Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM.

    상세보기
50. How Dana ; Srinivasan Adi ; El Gamal Abbas, Function block architecture for gate array.

    상세보기
51. Smith, Lyle; Dellinger, Eric; West, Eric; Mukund, Shridhar, Function block architecture with variable drive strengths.

    상세보기
52. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.

    상세보기
53. Chou, Shin-I, High-rate interpolation or decimation filter in integrated circuit device.

    상세보기
54. Martin Vorbach DE; Robert Munch DE, I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures.

    상세보기
55. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.

    상세보기
56. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.

    상세보기
57. Vorbach,Martin; M��nch,Robert, I/O and memory bus system for DFPS and units with two-or multi-dimensional programmable cell architectures.

    상세보기
58. Vorbach Martin,DEX ; Munch Robert,DEX, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.

    상세보기
59. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.

    상세보기
60. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.

    상세보기
61. Vorbach,Martin; M？nch,Robert, I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures.

    상세보기
62. Langhammer, Martin, Implementing division in a programmable integrated circuit device.

    상세보기
63. Langhammer, Martin, Implementing large multipliers in a programmable integrated circuit device.

    상세보기
64. Langhammer, Martin, Implementing mixed-precision floating-point operations in a programmable integrated circuit device.

    상세보기
65. Langhammer, Martin, Implementing multipliers in a programmable integrated circuit device.

    상세보기
66. Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.

    상세보기
67. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.

    상세보기
68. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.

    상세보기
69. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.

    상세보기
70. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.

    상세보기
71. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.

    상세보기
72. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

    상세보기
73. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

    상세보기
74. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

    상세보기
75. David W. Mendel ; Richard G. Cliff, Logic element for a programmable logic integrated circuit.

    상세보기
76. Mendel David W. ; Cliff Richard G., Logic element for a programmable logic integrated circuit.

    상세보기
77. Mendel David W. ; Cliff Richard G., Logic element for a programmable logic integrated circuit.

    상세보기
78. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.

    상세보기
79. Langhammer, Martin, Matrix decomposition in an integrated circuit device.

    상세보기
80. Kurtz, Brian L., Matrix operations in an integrated circuit device.

    상세보기
81. Langhammer, Martin, Matrix operations in an integrated circuit device.

    상세보기
82. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.

    상세보기
83. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.

    상세보기
84. Mauer, Volker; Demirsoy, Suleyman Sirri, Method for configuring a finite impulse response filter in a programmable logic device.

    상세보기
85. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).

    상세보기
86. Vorbach, Martin, Method for debugging reconfigurable architectures.

    상세보기
87. Vorbach, Martin, Method for debugging reconfigurable architectures.

    상세보기
88. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.

    상세보기
89. Vorbach,Martin, Method for debugging reconfigurable architectures.

    상세보기
90. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.

    상세보기
91. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.

    상세보기
92. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.

    상세보기
93. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.

    상세보기
94. Tharmalingam,Kumara, Method for programming programmable logic device having specialized functional blocks.

    상세보기
95. Vorbach Martin,DEX ; Munch Robert,DEX, Method for the automatic address generation of modules within clusters comprised of a plurality of these modules.

    상세보기
96. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.

    상세보기
97. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.

    상세보기
98. Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).

    상세보기
99. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).

    상세보기
100. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.

     상세보기
101. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.

     상세보기
102. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

     상세보기
103. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

     상세보기
104. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

     상세보기
105. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

     상세보기
106. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.

     상세보기
107. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.

     상세보기
108. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable unit.

     상세보기
109. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.

     상세보기
110. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

     상세보기
111. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

     상세보기
112. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

     상세보기
113. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.

     상세보기
114. Vorbach, Martin, Methods and devices for treating and/or processing data.

     상세보기
115. Langhammer, Martin, Methods for specifying processor architectures for programmable integrated circuits.

     상세보기
116. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.

     상세보기
117. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.

     상세보기
118. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.

     상세보기
119. Bulin, Tom; Gallagher, Tom; Gray, Scott E.; Langton, Gerard W., Monitoring system for a mobile storage tank.

     상세보기
120. Langhammer, Martin, Multi-operand floating point operations in a programmable integrated circuit device.

     상세보기
121. Reddy, Srinivas; Jefferson, David; Lane, Christopher F.; Santurkar, Vikram; Cliff, Richard, Multiple size memories in a programmable logic device.

     상세보기
122. Langhammer, Martin, Multiple-precision processing block in a programmable integrated circuit device.

     상세보기
123. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y., Multiplier-accumulator circuitry and methods.

     상세보기
124. Nance,Scott S.; Sheppard,Douglas P.; Sawyer,Nicholas J., Multiport RAM with programmable data port configuration.

     상세보기
125. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.

     상세보기
126. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.

     상세보기
127. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.

     상세보기
128. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.

     상세보기
129. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.

     상세보기
130. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.

     상세보기
131. Mauer, Volker; Langhammer, Martin, Pipelined systolic finite impulse response filter.

     상세보기
132. Langhammer, Martin, Polynomial calculations optimized for programmable integrated circuit device structures.

     상세보기
133. Vorbach Martin,DEX ; Munch Robert,DEX, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like).

     상세보기
134. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).

     상세보기
135. Martin Vorbach DE; Robert Munch DE, Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like).

     상세보기
136. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.

     상세보기
137. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.

     상세보기
138. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.

     상세보기
139. Sung Chiakang, Program compatibility recognition for a programmable logic device.

     상세보기
140. Langhammer, Martin, Programmable device using fixed and configurable logic to implement floating-point rounding.

     상세보기
141. Langhammer, Martin, Programmable device using fixed and configurable logic to implement recursive trees.

     상세보기
142. Mauer, Volker; Langhammer, Martin, Programmable device with specialized multiplier blocks.

     상세보기
143. Francis B. Heile, Programmable logic array device with random access memory configurable as product terms.

     상세보기
144. Heile Francis B., Programmable logic array device with random access memory configurable as product terms.

     상세보기
145. Heile Francis B., Programmable logic array device with random access memory configurable as product terms.

     상세보기
146. Heile, Francis B., Programmable logic array device with random access memory configurable as product terms.

     상세보기
147. Cliff Richard G. (Milpitas CA) Cope L. Todd (San Jose CA) McClintock Cameron R. (Mountain View CA) Leong William (San Francisco CA) Watson James A. (Santa Clara CA) Huang Joseph (San Jose CA) Ahanin , Programmable logic array integrated circuits.

     상세보기
148. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

     상세보기
149. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

     상세보기
150. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

     상세보기
151. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

     상세보기
152. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

     상세보기
153. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

     상세보기
154. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

     상세보기
155. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

     상세보기
156. Cliff, Richard G.; Ahanin, Bahram; Lytle, Craig Schilling; Heile, Francis B.; Pedersen, Bruce B.; Veenstra, Kerry, Programmable logic array integrated circuits.

     상세보기
157. Cliff, Richard G.; Cope, L. Todd; Mc Clintock, Cameron R.; Leong, William; Watson, James A.; Huang, Joseph; Ahanin, Bahram, Programmable logic array integrated circuits.

     상세보기
158. Lee Fung Fung ; Cliff Richard G. ; Cope L. Todd,MYX ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

     상세보기
159. Sasaki Paul T., Programmable logic device.

     상세보기
160. Tony K. Ngai ; Rakesh H. Patel ; Srinivas T. Reddy ; Richard G. Cliff, Programmable logic device having embedded dual-port random access memory configurable as single-port memory.

     상세보기
161. Langhammer, Martin; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.

     상세보기
162. Langhammer, Martin; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.

     상세보기
163. Langhammer,Martin; Hwang,Chiao Kai; Starr,Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.

     상세보기
164. Langhammer,Martin; Hwang,Chiao Kai; Starr,Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.

     상세보기
165. Reddy Srinivas T. ; Lane Christopher F. ; Mejia Manuel, Programmable logic device memory array circuit having combinable single-port memory arrays.

     상세보기
166. Reddy Srinivas T. ; Lane Christopher F. ; Mejia Manuel, Programmable logic device memory array circuit having combinable single-port memory arrays.

     상세보기
167. Langhammer, Martin, Programmable logic device with routing channels.

     상세보기
168. Langhammer,Martin, Programmable logic device with routing channels.

     상세보기
169. Langhammer,Martin, Programmable logic device with routing channels.

     상세보기
170. Langhammer,Martin, Programmable logic device with routing channels.

     상세보기
171. Langhammer, Martin; Zheng, Leon; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device with specialized functional block.

     상세보기
172. Langhammer, Martin; Zheng, Leon; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device with specialized functional block.

     상세보기
173. Langhammer, Martin, Programmable logic device with specialized multiplier blocks.

     상세보기
174. Agrawal,Om P.; Sharpe Geisler,Brad; Lee,Jye Yuh; Nguyen,Bai, Programmable logic devices with distributed memory and non-volatile memory.

     상세보기
175. Langhammer, Martin; Prasad, Nitin, Programmable logic devices with function-specific blocks.

     상세보기
176. Langhammer, Martin; Prasad, Nitin, Programmable logic devices with function-specific blocks.

     상세보기
177. Francis B. Heile, Programmable logic devices with improved content addressable memory capabilities.

     상세보기
178. Heile Francis B., Programmable logic devices with improved content addressable memory capabilities.

     상세보기
179. Sung Chiakang ; Huang Joseph ; Chang Wanli, Programming and verification address generation for random access memory blocks in programmable logic array integrated c.

     상세보기
180. Sung Chiakang ; Chang Wanli ; Huang Joseph ; Cliff Richard G. ; Cope L. Todd ; Leong ; deceased William ; Leong ; legal representative by Louis, Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices.

     상세보기
181. Langhammer, Martin, QR decomposition in an integrated circuit device.

     상세보기
182. Mauer, Volker, QR decomposition in an integrated circuit device.

     상세보기
183. Sung Chiakang (Milpitas CA) Chang Wanli (Saratoga CA) Huang Joseph (San Jose CA) Cliff Richard G. (Milpitas CA), Random access memory block circuitry for programmable logic array integrated circuit devices.

     상세보기
184. Vorbach, Martin, Reconfigurable elements.

     상세보기
185. Vorbach, Martin, Reconfigurable elements.

     상세보기
186. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.

     상세보기
187. Vorbach,Martin; M？nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.

     상세보기
188. Vorbach, Martin, Reconfigurable sequencer structure.

     상세보기
189. Vorbach, Martin, Reconfigurable sequencer structure.

     상세보기
190. Vorbach, Martin, Reconfigurable sequencer structure.

     상세보기
191. Vorbach, Martin, Reconfigurable sequencer structure.

     상세보기
192. Vorbach,Martin, Reconfigurable sequencer structure.

     상세보기
193. Vorbach, Martin; Bretz, Daniel, Router.

     상세보기
194. Vorbach,Martin; Bretz,Daniel, Router.

     상세보기
195. Vorbach Martin,DEX ; Munch Robert,DEX, Run-time reconfiguration method for programmable units.

     상세보기
196. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.

     상세보기
197. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.

     상세보기
198. Durbeck Lisa J. K. ; Macias Nicholas J., Self-configurable parallel processing system made from self-dual code/data processing cells utilizing a non-shifting memory.

     상세보기
199. Langhammer, Martin; Dhanoa, Kulwinder, Solving linear matrices in an integrated circuit device.

     상세보기
200. Langhammer, Martin, Specialized processing block for implementing floating-point multiplier with subnormal operation support.

     상세보기
201. Xu, Lei; Mauer, Volker; Perry, Steven, Specialized processing block for programmable integrated circuit device.

     상세보기
202. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Lin, Yi-Wen, Specialized processing block for programmable logic device.

     상세보기
203. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Pelt, Robert L., Specialized processing block for programmable logic device.

     상세보기
204. Langhammer, Martin; Lee, Kwan Yee Martin; Nguyen, Triet M.; Streicher, Keone; Azgomi, Orang, Specialized processing block for programmable logic device.

     상세보기
205. Lee, Kwan Yee Martin; Langhammer, Martin; Lin, Yi-Wen; Nguyen, Triet M., Specialized processing block for programmable logic device.

     상세보기
206. Lee, Kwan Yee Martin; Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Specialized processing block for programmable logic device.

     상세보기
207. Langhammer, Martin, Specialized processing block with fixed- and floating-point structures.

     상세보기
208. Andy Lee, Static random access memory circuits.

     상세보기
209. Lee Andy, Static random access memory circuits.

     상세보기
210. Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.

     상세보기
211. Sung, Chiakang; Chang, Wanli; Huang, Joseph; Cliff, Richard G.; Cope, L. Todd; McClintock, Cameron R.; Leong, William; Watson, James A.; Ahanin, Bahram, Variable depth and width memory device.

     상세보기
212. Pedersen Bruce B., Variable depth memories for programmable logic devices.

     상세보기
213. Pedersen,Bruce B, Versatile RAM for a programmable logic device.

     상세보기
214. Pedersen,Bruce B, Versatile RAM for programmable logic device.

     상세보기
더보기