이 특허를 인용한 특허 (261) 인용/피인용 타임라인 분석

1. Crane ; Jr. Stanford W. ; Larcomb Daniel ; Krishnapura Lakshminarasimha, Apparatus for and method of manufacturing a semiconductor die carrier.

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2. Crane, Jr., Stanford W.; Larcomb, Daniel; Krishnapura, Lakshminarasimha, Apparatus for and method of manufacturing a semiconductor die carrier.

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3. Kang,Teck Gyu; Kubota,Yoichi, Assemblies having stacked semiconductor chips and methods of making same.

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4. Caskey, Terrence; Mohammed, Ilyas; Uzoh, Cyprian Emeka; Woychik, Charles G.; Newman, Michael; Monadgemi, Pezhman; Co, Reynaldo; Chau, Ellis; Haba, Belgacem, BVA interposer.

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5. Subido, Willmar; Co, Reynaldo; Zohni, Wael; Prabhu, Ashok S., Ball bonding metal wire bond wires to metal pads.

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6. Haba, Belgacem; Mohammed, Ilyas; Wang, Liang, Batch process fabrication of package-on-package microelectronic assemblies.

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7. Haba, Belgacem; Mohammed, Ilyas; Wang, Liang, Batch process fabrication of package-on-package microelectronic assemblies.

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8. Haba, Belgacem; Mohammed, Ilyas; Wang, Liang, Batch process fabrication of package-on-package microelectronic assemblies.

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9. Katkar, Rajesh; Gao, Guilian; Woychik, Charles G.; Zohni, Wael, Bond via array for thermal conductivity.

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10. Imamura,Hiroyuki; Koutani,Nobuyuki; Nakamura,Yoshifumi; Tokushima,Kenshi, Circuit board with auxiliary wiring configuration to suppress breakage during bonding process.

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11. Kubota,Yoichi; Kang,Teck Gyu; Park,Jae M.; Haba,Belgacem, Components with posts and pads.

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12. Vidal Ulrich,DEX, Composite member composed of at least two integrated circuits and method for the manufacture of a composite member composed of at least two integrated circuits.

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13. Uzoh, Cyprian Emeka; Katkar, Rajesh, Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects.

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14. Wood,Alan G.; Cloud,Eugene H.; Kinsman,Larry D., Double-packaged multi-chip semiconductor module.

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15. Wood, Alan G.; Cloud, Eugene H.; Kinsman, Larry D., Double-packaged multichip semiconductor module.

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16. Co, Reynaldo; Leal, Jeffrey S.; Pangrle, Suzette K.; McGrath, Scott; Melcher, De Ann Eileen; Barrie, Keith L.; Villavicencio, Grant; Del Rosario, Elmer M.; Bray, John R., Electrical connector between die pad and z-interconnect for stacked die assemblies.

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17. Co, Reynaldo; Leal, Jeffrey S.; Pangrle, Suzette K.; McGrath, Scott; Melcher, DeAnn Eileen; Barrie, Keith L.; Villavicencio, Grant; del Rosario, Elmer M.; Bray, John R., Electrical connector between die pad and z-interconnect for stacked die assemblies.

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18. Co, Reynaldo; Villavicencio, Grant; Leal, Jeffrey S.; McElrea, Simon J. S., Electrical interconnect for die stacked in zig-zag configuration.

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19. McElrea, Simon J. S.; Andrews, Jr., Lawrence Douglas; McGrath, Scott; Caskey, Terrence; Crane, Scott Jay; Robinson, Marc E.; Cantillep, Loreto, Electrically interconnected stacked die assemblies.

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20. McElrea, Simon J. S.; Andrews, Jr., Lawrence Douglas; McGrath, Scott; Caskey, Terrence; Crane, Scott Jay; Robinson, Marc E.; Cantillep, Loreto, Electrically interconnected stacked die assemblies.

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21. Kanekawa, Nobuyasu; Ihara, Hirokazu; Akiyama, Masatsugu; Kawabata, Kiyoshi; Yamanaka, Hisayoshi; Okishima, Tetsuya, Electronic circuit package.

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22. Kanekawa,Nobuyasu; Ihara,Hirokazu; Akiyama,Masatsugu; Kawabata,Kiyoshi; Yamanaka,Hisayoshi; Okishima,Tetsuya, Electronic circuit package.

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23. Kenneth J. Kledzik ; Jason C. Engle, Electronic module having a three dimensional array of carrier-mounted integrated circuit packages.

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24. DeLaCruz, Javier A.; Awujoola, Abiola; Prabhu, Ashok S.; Lattin, Christopher W.; Sun, Zhuowen, Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces.

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25. Tao, Min; Sun, Zhuowen; Kim, Hoki; Zohni, Wael; Agrawal, Akash, Enhanced density assembly having microelectronic packages mounted at substantial angle to board.

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26. Haba, Belgacem; Zohni, Wael; Crisp, Richard Dewitt, Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics.

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27. Haba, Belgacem; Mohammed, Ilyas, Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation.

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28. Miyano Ichiro,JPX ; Serizawa Koji,JPX ; Tanaka Hiroyuki,JPX ; Shinoda Tadao,JPX ; Sakaguchi Suguru,JPX, Film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof.

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29. Katkar, Rajesh, Fine pitch BVA using reconstituted wafer with area array accessible for testing.

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30. Katkar, Rajesh, Fine pitch BVA using reconstituted wafer with area array accessible for testing.

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31. Haba, Belgacem; Kubota, Yoichi; Kang, Teck-Gyu; Park, Jae M., Fine pitch microcontacts and method for forming thereof.

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32. Kwon, Jinsu, Flip chip interconnection with double post.

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33. Haba, Belgacem; Crisp, Richard Dewitt; Zohni, Wael, Flip-chip, face-up and face-down centerbond memory wirebond assemblies.

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34. Katkar, Rajesh; Co, Reynaldo; McGrath, Scott; Prabhu, Ashok S.; Lee, Sangil; Wang, Liang; Shen, Hong, Flipped die stack.

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35. Prabhu, Ashok S.; Katkar, Rajesh; Wang, Liang; Uzoh, Cyprian Emeka, Flipped die stack assemblies with leadframe interconnects.

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36. Delacruz, Javier A.; Haba, Belgacem; Vu, Tu Tam; Katkar, Rajesh, Flipped die stacks with multiple rows of leadframe interconnects.

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37. Delacruz, Javier A.; Haba, Belgacem; Vu, Tu Tam; Katkar, Rajesh, Flipped die stacks with multiple rows of leadframe interconnects.

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38. Haba, Belgacem; Beroz, Masud; Kim, Young-Gon; Tuckerman, David B., Formation of circuitry with modification of feature height.

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39. Haba,Belgacem; Beroz,Masud; Kim,Young Gon; Tuckerman,David B., Formation of circuitry with modification of feature height.

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40. Mohammed, Ilyas; Beroz, Masud, Heat spreading substrate with embedded interconnects.

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41. Koh,Wei H.; Chen,David, High density memory card assembly.

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42. Michii, Kazunari, Integrated circuits substrate.

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43. Bertin Claude Louis (South Burlington VT) Howell Wayne John (South Burlington VT) Hedberg Erik Leigh (Essex Junction VT) Kalter Howard Leo (Colchester VT) Kelley ; Jr. Gordon Arthur (Essex Junction V, Integrated mulitchip memory module, structure and fabrication.

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44. Gupta, Debabrata; Hashimoto, Yukio; Mohammed, Ilyas; Mirkarimi, Laura Wills; Katkar, Rajesh, Interconnect structure.

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45. Gupta, Debabrata; Hashimoto, Yukio; Mohammed, Ilyas; Mirkarimi, Laura; Katkar, Rajesh, Interconnect structure.

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46. Hoshino, Hitoshi; Sato, Tomiji; Taga, Atsushi, LSI package and internal connecting method used therefor.

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47. Hoshino, Hitoshi; Sato, Tomiji; Taga, Atsushi, LSI package with internal wire patterns to connect and mount bare chip to substrate.

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48. Katkar, Rajesh; Uzoh, Cyprian Emeka, Low CTE component with wire bond interconnects.

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49. Katkar, Rajesh; Uzoh, Cyprian Emeka, Low CTE component with wire bond interconnects.

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50. Vincent DiCaprio ; Sean T. Crowley ; J. Mark Bird, Low profile package for plural semiconductor dies.

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51. Mosley Joseph M. ; Portuondo Maria M. ; Taylor Drew L., Low profile semiconductor die carrier.

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52. Fukasawa, Norio; Kawahara, Toshimi; Morioka, Muneharu; Osawa, Mitsunada; Shinma, Yasuhiro; Matsuki, Hirohisa; Onodera, Masanori; Kasai, Junichi; Maruyama, Shigeyuki; Sakuma, Masao; Suzuki, Yoshimi; T, Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device.

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53. Vindasius Alfons ; Sautter Kenneth M., Method for forming vertical interconnect process for silicon segments with dielectric isolation.

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54. Vindasius Alfons ; Sautter Kenneth M., Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform.

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55. Val Christian (St Remy les Chevreuse FRX), Method for interconnecting semiconductor chips in three dimensions, and component resulting therefrom.

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56. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Method for making a microelectronic assembly having conductive elements.

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57. Karnezos,Marcos, Method for making a semiconductor multipackage module including a processor and memory package assemblies.

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58. Co, Reynaldo; Mirkarimi, Laura, Method for package-on-package assembly with wire bonds to encapsulation surface.

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59. Co, Reynaldo; Mirkarimi, Laura, Method for package-on-package assembly with wire bonds to encapsulation surface.

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60. Karnezos, Marcos, Method of fabricating a semiconductor multi package module having an inverted package stacked over ball grid array (BGA) package.

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61. Karnezos, Marcos, Method of fabricating a semiconductor multipackage module including a processor and memory package assemblies.

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62. Zhao, Zhijun; Alatorre, Roseann, Method of forming a component having wire bonds and a stiffening layer.

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63. Chiang, Cheng-Lien, Method of forming a three-dimensional stacked semiconductor package device.

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64. Mohammed, Ilyas, Method of forming a wire bond having a free end.

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65. Iijima Makoto,JPX ; Wakabayashi Tetsushi,JPX ; Hamano Toshio,JPX ; Minamizawa Masaharu,JPX ; Takenaka Masashi,JPX ; Yamashita Taturou,JPX ; Mizukoshi Masataka,JPX, Method of forming an assembly board with insulator filled through holes.

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66. Kubota, Yoichi; Kang, Teck-Gyu; Park, Jae M.; Haba, Belgacem, Method of making a connection component with posts and pads.

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67. Kubota, Yoichi; Kang, Teck-Gyu; Park, Jae M.; Haba, Belgacem, Method of making a connection component with posts and pads.

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68. Lin, Charles W. C., Method of making a semiconductor chip assembly with chip and encapsulant grinding.

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69. Lin, Charles W. C.; Wang, Chia-Chung; Sigmond, David M., Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment.

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70. Lin,Charles W. C.; Wang,Chia Chung, Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding.

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71. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture.

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72. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture.

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73. Crane ; Jr. Stanford W. ; Portuondo Maria M., Method of manufacturing a semiconductor chip carrier.

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74. Rinne Glenn A. ; Lizzul Christine, Methods of electroplating solder bumps of uniform height on integrated circuit substrates.

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75. Igor Y. Khandros ; Thomas H. Distefano, Methods of making semiconductor chip assemblies.

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76. Damberg, Philip; Haba, Belgacem; Tuckerman, David B.; Kang, Teck-Gyu, Micro pin grid array with pin motion isolation.

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77. Damberg, Philip; Haba, Belgacem; Tuckerman, David B.; Kang, Teck-Gyu, Micro pin grid array with pin motion isolation.

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78. Mohammed, Ilyas; Haba, Belgacem, Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation.

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79. Mohammed, Ilyas; Haba, Belgacem, Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation.

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80. Haba, Belgacem; Mitchell, Craig S., Microelectronic assemblies having very fine pitch stacking.

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81. Mohammed, Ilyas; Haba, Belgacem, Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation.

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82. Haba, Belgacem; Mohammed, Ilyas; Caskey, Terrence; Co, Reynaldo; Chau, Ellis, Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface.

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83. Pflughaupt,L. Elliott; Gibson,David; Kim,Young Gon; Mitchell,Craig S.; Zohni,Wael; Mohammed,Ilyas, Microelectronic assembly having array including passive elements and interconnects.

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84. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.

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85. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.

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86. Haba, Belgacem; Crisp, Richard Dewitt; Zohni, Wael, Microelectronic element with bond elements to encapsulation surface.

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87. Mohammed, Ilyas; Haba, Belgacem; Moran, Sean; Wang, Wei-Shun; Chau, Ellis; Wade, Christopher, Microelectronic package.

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88. Haba, Belgacem; Beroz, Masud; Humpston, Giles; Park, Jae M., Microelectronic package comprising offset conductive posts on compliant layer.

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89. Prabhu, Ashok S.; Katkar, Rajesh, Microelectronic package for wafer-level chip scale packaging with fan-out.

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90. Haba, Belgacem, Microelectronic package with terminals on dielectric mass.

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91. Haba, Belgacem, Microelectronic package with terminals on dielectric mass.

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92. Haba, Belgacem, Microelectronic package with terminals on dielectric mass.

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93. Haba, Belgacem, Microelectronic package with terminals on dielectric mass.

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94. Haba, Belgacem; Sun, Zhuowen; Delacruz, Javier A., Microelectronic packages and assemblies with improved flyby signaling operation.

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95. Haba, Belgacem; Beroz, Masud; Green, Ronald; Mohammed, Ilyas; Wilson, Stuart E.; Zohni, Wael; Kubota, Yoichi; Thompson, Jesse Burl, Microelectronic packages and methods therefor.

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96. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Microelectronic packages and methods therefor.

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97. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Microelectronic packages and methods therefor.

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98. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Microelectronic packages and methods therefor.

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99. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Microelectronic packages and methods therefor.

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100. Haba,Belgacem; Beroz,Masud; Green,Ronald; Mohammed,Ilyas; Wilson,Stuart E.; Zohni,Wael; Kubota,Yoichi; Thompson,Jesse Burl, Microelectronic packages and methods therefor.

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101. Haba, Belgacem, Microelectronic packages with dual or multiple-etched flip-chip connectors.

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102. Haba, Belgacem, Microelectronic packages with dual or multiple-etched flip-chip connectors.

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103. Haba, Belgacem, Microelectronic packages with nanoparticle joining.

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104. Haba, Belgacem, Microelectronic packages with nanoparticle joining.

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105. Haba, Belgacem, Microelectronic packages with nanoparticle joining.

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106. Bang,Kyong Mo; Kang,Teck Gyu; Park,Jae M., Microelectronic packages with self-aligning features.

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107. Crane ; Jr. Stanford W. ; Krishnapura Lakshminarasimha ; Li Yun ; Behar Moises ; Fuoco Dan ; Ahearn Bill, Multi-chip module having interconnect dies.

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108. Crane ; Jr. Stanford W. ; Krishnapura Lakshminarasimha ; Li Yun ; Behar Moises ; Fuoco Dan ; Ahearn Bill, Multi-chip module having interconnect dies.

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109. Koh, Wei H.; Chen, David H., Multi-level package for a memory module.

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110. Matsunaga Hayami (Hirakata JPX) Iwata Masao (Hirakata JPX) Suehiro Yoshikazu (Ikoma JPX) Kurokawa Hideo (Hirakata JPX) Okamoto Izumi (Osaka JPX), Multilevel semiconductor integrated circuit device.

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111. Uzoh, Cyprian Emeka; Katkar, Rajesh, Multiple bond via arrays of different wire heights on a same substrate.

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112. Uzoh, Cyprian Emeka; Katkar, Rajesh, Multiple bond via arrays of different wire heights on a same substrate.

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113. Haba, Belgacem; Zohni, Wael; Crisp, Richard Dewitt; Mohammed, Ilyas; Lambrecht, Frank, Multiple die face-down stacking for two or more die.

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114. Foster, Donald C., Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring.

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115. Zohni, Wael; Haba, Belgacem, Multiple die stacking for two or more die.

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116. Zohni, Wael; Haba, Belgacem, Multiple die stacking for two or more die.

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117. Jiang,Tongbi; Brooks,J. Michael, Multiple substrate microelectronic devices and methods of manufacture.

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118. Haba, Belgacem; Co, Reynaldo; Cizek, Rizza Lee Saga; Zohni, Wael, Off substrate kinking of bond wire.

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119. Haba, Belgacem; Co, Reynaldo; Saga Cizek, Rizza Lee; Zohni, Wael, Off substrate kinking of bond wire.

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120. Il Kwon Shim SG; Vincent DiCaprio ; Paul Hoffman ; Byung Joon Han SG, Package for stacked integrated circuits.

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121. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.

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122. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.

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123. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.

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124. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.

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125. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.

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126. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young; Zhao, Zhijun, Package-on-package assembly with wire bond vias.

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127. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.

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128. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.

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129. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.

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130. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.

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131. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.

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132. Prabhu, Ashok S.; Katkar, Rajesh, Packaged microelectronic device for a package-on-package device.

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133. Damberg, Philip; Colella, Nicholas J., Packaged systems with MRAM.

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134. Haba, Belgacem; Mohammed, Ilyas, Pin attachment.

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135. Crane, Jr., Stanford W.; Portuondo, Maria M., Prefabricated semiconductor chip carrier.

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136. Stanford W. Crane, Jr. ; Maria M. Portuondo, Prefabricated semiconductor chip carrier.

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137. Co, Reynaldo; Villavicencio, Grant; Zohni, Wael, Pressing of wire bond wire tips to provide bent-over tips.

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138. Mohammed, Ilyas, Reconstituted wafer-level package DRAM.

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139. Mohammed, Ilyas, Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package.

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140. Satoshi Oguchi JP; Masamichi Ishihara JP; Kazuya Ito JP; Gen Murakami JP; Ichiro Anjoh JP; Toshiyuki Sakuta JP; Yasunori Yamaguchi JP; Yasuhiro Kasama JP; Tetsu Udagawa JP; Eiji Momose JP; , Sealed stacked arrangement of semiconductor devices.

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141. Leal, Jeffrey S., Selective die electrical insulation by additive process.

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142. Leal, Jeffrey S., Selective die electrical insulation by additive process.

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143. Khandros,Igor Y.; DiStefano,Thomas H., Semiconductor chip assemblies, methods of making same and components for same.

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144. Khandros,Igor Y.; Distefano,Thomas H., Semiconductor chip assemblies, methods of making same and components for same.

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145. Ikemoto Masahiko,JPX, Semiconductor component.

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146. Horio, Masafumi; Fukuda, Kyohei; Hori, Motohito; Ikeda, Yoshinari, Semiconductor device.

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147. Yamazaki, Takashi; Endo, Mitsuyoshi; Takubo, Chiaki; Oyama, Katsuhiko; Imoto, Takashi; Matsui, Mikio, Semiconductor device.

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148. Iijima Makoto,JPX ; Wakabayashi Tetsushi,JPX ; Hamano Toshio,JPX ; Minamizawa Masaharu,JPX ; Takenaka Masashi,JPX ; Yamashita Taturou,JPX ; Mizukoshi Masataka,JPX, Semiconductor device and assembly board having through-holes filled with filling core.

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149. Fujisawa Tetsuya,JPX ; Sato Mitsutaka,JPX ; Kasai Junichi,JPX ; Mizukoshi Masataka,JPX ; Otokita Kosuke,JPX ; Yoshimura Hiroshi,JPX ; Hayashida Katsuhiro,JPX ; Takashima Akira,JPX ; Ishiguri Masahiko, Semiconductor device and semiconductor device unit for a stack arrangement.

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150. Corisis, David J.; Chong, Chin Hui; Lee, Choon Kuan, Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device.

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151. Tomita Yoshihiro,JPX, Semiconductor device comprising stacked semiconductor elements.

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152. Tanaka, Shuichi, Semiconductor device having a resin protrusion with a depression and method manufacturing the same.

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153. Fujisawa Tetsuya,JPX ; Sato Mitsutaka,JPX ; Kasai Junichi,JPX ; Mizukoshi Masataka,JPX ; Otokita Kousuke,JPX ; Yoshimura Hiroshi,JPX ; Hayashida Katsuhiro,JPX ; Takashima Akira,JPX ; Ishiguri Masahik, Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plasti.

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154. Murakamz Gen,JPX ; Mita Mamoru,JPX ; Okabe Norio,JPX ; Kameyama Yasuharu,JPX, Semiconductor device, tab tape for semiconductor device, method of manufacturing the tab tape and method of manufacturing the semiconductor device.

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155. Co, Reynaldo; Melcher, DeAnn Eileen; Pan, Weiping; Villavicencio, Grant, Semiconductor die array structure.

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156. Mosley Joseph M. ; Portuondo Maria M., Semiconductor die carrier having a dielectric epoxy between adjacent leads.

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157. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, De Ann Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.

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158. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, De Ann Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.

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159. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, DeAnn Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.

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160. Crane ; Jr. Stanford W. ; Krishnapura Lakshminarasimha, Semiconductor die package for mounting in horizontal and upright configurations.

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161. Masayuki, Watanabe; Toshio, Sugano; Seiichiro, Tsukui; Takashi, Ono; Yoshiaki, Wakashima, Semiconductor memory module having double-sided stacked memory chip layout.

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162. Masayuki, Watanabe; Toshio, Sugano; Seiichiro, Tsukui; Takashi, Ono; Yoshiaki, Wakashima, Semiconductor memory module having double-sided stacked memory chip layout.

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163. Matsuura, Tetsuya; Kasatani, Yasushi; Michii, Kazunari; Maeda, Hajime, Semiconductor module and electronic component.

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164. Cheng-Lien Chiang TW, Semiconductor module with encapsulant base.

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165. Karnezos,Marcos, Semiconductor multipackage module including processor and memory package assemblies.

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166. Shin, Won Sun; Lee, Seon Goo; Chun, Do Sung; Jang, Tae Hoan; DiCaprio, Vincent D., Semiconductor package and method for fabricating the same.

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167. Shin,Won Sun; Chun,Do Sung; Lee,Sang Ho; Lee,Seon Goo; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.

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168. Shin,Won Sun; Chun,Do Sung; Lee,Soon Goo; Shim,Il Kwon; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.

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169. Shin,Won Sun; Lee,Seon Goo; Chun,Do Sung; Jang,Tae Hoan; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.

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170. WonSun Shin KR; DoSung Chun TH; SangHo Lee KR; SeonGoo Lee KR; Vincent DiCaprio, Semiconductor package and method for fabricating the same.

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171. Shin, WonSun; Chun, DoSung; Lee, SangHo; Lee, SeonGoo; DiCaprio, Vincent, Semiconductor package having semiconductor chip within central aperture of substrate.

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172. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.

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173. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.

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174. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package including stacked chips with aligned input/output pads.

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175. Heo,Byong II, Semiconductor package with substrate coupled to a peripheral side surface of a semiconductor die.

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176. Sekiguchi,Tomonori; Osaka,Hideki; Ido,Tatemi; Nagashima,Osamu; Katagiri,Mitsuaki; Anjo,Ichiro, Semiconductor storage device having a plurality of stacked memory chips.

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177. Kawamura, Masayasu; Nakamura, Atsushi; Sakaguchi, Yoshihiro; Kinoshita, Yoshitaka; Takahashi, Yasushi; Inoue, Yoshihiko, Semiconductor storage device having memory chips in a stacked structure.

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178. Haba, Belgacem; Co, Reynaldo; Saga Cizek, Rizza Lee; Zohni, Wael, Severing bond wire by kinking and twisting.

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179. David V. Pedersen ; Michael G. Finley ; Kenneth M. Sautter, Silicon segment programming apparatus and three terminal fuse configuration.

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180. Pedersen David V. ; Finley Michael G. ; Sautter Kenneth M., Silicon segment programming method.

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181. Pedersen David V. (Scotts Valley CA) Finley Michael G. (Cambria CA) Sautter Kenneth M. (Sunnyvale CA), Silicon segment programming method and apparatus.

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182. Wilson, Stuart E.; Green, Ronald; Crisp, Richard Dewitt; Humpston, Giles, Stack microelectronic assemblies.

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183. Haba, Belgacem, Stackable molded microelectronic packages.

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184. Haba, Belgacem, Stackable molded microelectronic packages.

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185. Haba, Belgacem, Stackable molded microelectronic packages.

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186. Haba, Belgacem, Stackable molded microelectronic packages.

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187. Haba, Belgacem, Stackable molded microelectronic packages.

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188. Haba, Belgacem, Stackable molded microelectronic packages with area array unit connectors.

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189. Haba, Belgacem, Stackable molded microelectronic packages with area array unit connectors.

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190. Shin,WonSun; Chun,DoSung; Lee,SangHo; Lee,SeonGoo; DiCaprio,Vincent, Stackable semiconductor package having semiconductor chip within central through hole of substrate.

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191. Bellaar Pieter H.,NLX, Stacked chip assembly.

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192. Igor Y. Khandros ; Thomas H. DiStefano, Stacked chip assembly.

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193. Zohni, Wael; Haba, Belgacem, Stacked chip-on-board module with edge connector.

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194. McGrath, Scott; Leal, Jeffrey S.; Shenoy, Ravi; Cantillep, Loreto; McElrea, Simon; Pangrle, Suzette K., Stacked die assembly having reduced stress electrical interconnects.

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195. Choh, Thong Kai; Khor, Lily; Yee, Oo Choo, Stacked electronic packages.

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196. Ogata Masatsugu (Hitachi JPX) Kitamura Teruo (Katsuta JPX) Eguchi Shuji (Ibaraki-ken JPX) Akeyama Kenji (Gunma-ken JPX), Stacked high mounting density semiconductor devices.

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197. Gibson, David; Stavros, Andy, Stacked microelectronic assemblies.

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198. Gibson, David; Stavros, Andy, Stacked microelectronic assemblies.

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199. Warner,Michael; Damberg,Philip; Riley,John B.; Gibson,David; Kim,Young Gon; Haba,Belgacem; Solberg,Vernon, Stacked microelectronic assemblies.

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200. Damberg, Philip; Mitchell, Craig S.; Riley, John B.; Warner, Michael; Fjelstad, Joseph, Stacked microelectronic assemblies and methods of making same.

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201. Haba, Belgacem, Stacked microelectronic assemblies with central contacts.

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202. Kim, Young; Haba, Belgacem; Solberg, Vernon, Stacked microelectronic assembly and method therefor.

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203. Solberg Vernon, Stacked microelectronic assembly and method therefor.

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204. Corisis, David J., Stacked microelectronic device assemblies.

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205. Corisis,David J., Stacked microelectronic dies.

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206. Corisis, David J., Stacked microelectronic dies and methods for stacking microelectronic dies.

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207. Kang Kyung Suk,KRX, Stacked package of semiconductor package units via direct connection between leads and stacking method therefor.

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208. Pflughaupt, L. Elliott; Gibson, David; Kim, Young-Gon; Mitchell, Craig S., Stacked packages.

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209. Pflughaupt, L. Elliott; Gibson, David; Kim, Young-Gon; Mitchell, Craig S., Stacked packages.

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210. Pflughaupt, L. Elliott; Gibson, David; Kim, Young-Gon; Mitchell, Craig S.; Zohni, Wael; Mohammed, Ilyas, Stacked packages.

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211. Gibson, David; Stavros, Andy, Stacked packages and microelectronic assemblies incorporating the same.

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212. Gibson,David; Stavros,Andy, Stacked packages and systems incorporating the same.

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213. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.

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214. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.

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215. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.

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216. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.

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217. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.

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218. Ohuchi Shinji,JPX, Stacked semiconductor device.

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219. Chiou, Ren-Kang; Chu, Tzu-Yih, Stacking memory chips using flat lead-frame with breakaway insertion pins and pin-to-pin bridges.

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220. Villavicencio, Grant; Lee, Sangil; Alatorre, Roseann; Delacruz, Javier A.; McGrath, Scott, Stiffened wires for offset BVA.

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221. Haba, Belgacem; Mohammed, Ilyas; Caskey, Terrence; Co, Reynaldo; Chau, Ellis, Structure for microelectronic packaging with bond elements to encapsulation surface.

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222. Haba, Belgacem; Mohammed, Ilyas; Caskey, Terrence; Co, Reynaldo; Chau, Ellis, Structure for microelectronic packaging with bond elements to encapsulation surface.

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223. Haba, Belgacem; Mohammed, Ilyas, Structure for microelectronic packaging with terminals on dielectric mass.

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224. Uzoh, Cyprian Emeka, Structures and methods for low temperature bonding using nanoparticles.

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225. Uzoh, Cyprian Emeka, Structures and methods for low temperature bonding using nanoparticles.

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226. Mohammed, Ilyas, Substrate-less stackable package with wire-bond interconnect.

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227. Mohammed, Ilyas, Substrate-less stackable package with wire-bond interconnect.

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228. Mohammed, Ilyas, Substrate-less stackable package with wire-bond interconnect.

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229. McElrea, Simon J. S.; Robinson, Marc E.; Andrews, Jr., Lawrence Douglas, Support mounted electrically interconnected die assembly.

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230. Park Bum-yeul,KRX, Tape automated bonding (tab) tapes having underlying camber suppressing films to inhibit warping.

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231. Juskey,Frank J.; Lau,Daniel K., Thin multiple semiconductor die package.

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232. Shin,Won Sun; Chun,Do Sung; Lee,Seon Goo; Shim,Il Kwon; DiCaprio,Vincent, Thin semiconductor package including stacked dies.

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233. Lyu, Ju Hyun; Lee, Kwan Jai; Cho, Tae Je, Thin stacked package.

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234. Lyu, Ju Hyun; Lee, Kwan Jai; Cho, Tae Je, Thin stacked package and manufacturing method thereof.

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235. Hawke Robert E.,CAX ; Patel Atin J.,CAX ; Binapal Sukhminder S.,CAX ; Divita Charles,CAX ; McNeil Lynn,CAX ; Fletcher Thomas G.,CAX, Three dimensional packaging configuration for multi-chip module assembly.

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236. Sadeg M. Faris, Three-dimensional packaging technology for multi-layered integrated circuits.

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237. Charles W.C. Lin SG, Three-dimensional stacked semiconductor package.

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238. Lin, Charles W. C., Three-dimensional stacked semiconductor package.

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239. Lin, Charles W. C., Three-dimensional stacked semiconductor package.

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240. Chiang,Cheng Lien, Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same.

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241. Chiang,Cheng Lien, Three-dimensional stacked semiconductor package with chips on opposite sides of lead.

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242. Lin,Charles W. C.; Chiang,Cheng Lien, Three-dimensional stacked semiconductor package with metal pillar in encapsulant aperture.

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243. Lin, Charles W. C.; Chiang, Cheng-Lien; Sigmond, David M., Three-dimensional stacked semiconductor package with pillars in pillar cavities.

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244. McElrea, Simon; Zohni, Wael; Haba, Belgacem, Through interposer wire bond using low CTE interposer with coarse slot apertures.

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245. Caskey, Terrence; Andrews, Jr., Lawrence Douglas; McGrath, Scott; McElrea, Simon J. S.; Du, Yong; Scott, Mark, Vertical electrical interconnect formed on support prior to die mount.

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246. Pedersen David V. (Scotts Valley CA) Finley Michael G. (Cambria CA) Sautter Kenneth M. (Sunnyvale CA), Vertical interconnect process for silicon segments.

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247. Pedersen David V. ; Finley Michael G. ; Sautter Kenneth M., Vertical interconnect process for silicon segments.

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248. Pedersen David V. ; Finley Michael G. ; Sautter Kenneth M., Vertical interconnect process for silicon segments.

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249. Vindasius Alfons ; Sautter Kenneth M., Vertical interconnect process for silicon segments with dielectric isolation.

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250. Vindasius Alfons ; Sautter Kenneth M., Vertical interconnect process for silicon segments with thermally conductive epoxy preform.

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251. Prabhu, Ashok S.; Katkar, Rajesh; Moran, Sean, Wafer-level flipped die stacks with leadframes or metal foil interconnects.

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252. Prabhu, Ashok S.; Katkar, Rajesh; Moran, Sean, Wafer-level flipped die stacks with leadframes or metal foil interconnects.

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253. Katkar, Rajesh; Vu, Tu Tam; Lee, Bongsub; Bang, Kyong-Mo; Li, Xuan; Huynh, Long; Guevara, Gabriel Z.; Agrawal, Akash; Subido, Willmar; Mirkarimi, Laura Wills, Wafer-level packaging using wire bond wires in place of a redistribution layer.

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254. Co, Reynaldo; Zohni, Wael; Cizek, Rizza Lee Saga; Katkar, Rajesh, Wire bond support structure and microelectronic package including wire bonds therefrom.

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255. Co, Reynaldo; Zohni, Wael; Saga Cizek, Rizza Lee; Katkar, Rajesh, Wire bond support structure and microelectronic package including wire bonds therefrom.

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256. Awujoola, Abiola; Sun, Zhuowen; Zohni, Wael; Prabhu, Ashok S.; Subido, Willmar, Wire bond wires for interference shielding.

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257. Awujoola, Abiola; Sun, Zhuowen; Zohni, Wael; Prabhu, Ashok S.; Subido, Willmar, Wire bond wires for interference shielding.

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258. Huang, Shaowu; Delacruz, Javier A., Wire bonding method and apparatus for electromagnetic interference shielding.

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259. Park, Young Kuk; Han, Byung Joon; Kim, Jae Dong, Wire bonding method and semiconductor package manufactured using the same.

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260. Park, Young Kuk; Han, Byung Joon; Kim, Jae Dong, Wire bonding method for a semiconductor package.

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261. Prabhu, Ashok S.; Katkar, Rajesh, ‘RDL-First’ packaged microelectronic device for a package-on-package device.

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