[특허]Distributed architecture for input/output for a multiprocessor system

[미국특허] Distributed architecture for input/output for a multiprocessor system 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-015/16
출원번호	US-0536182 (1990-06-11)
발명자 / 주소	Miller Edward C. (Eau Claire WI) Chen Steve S. (Chippewa Falls WI) Simmons Frederick J. (Neillsville WI) Spix George A. (Eau Claire WI) Veil Leonard S. (Eau Claire WI) Vogel Mark J. (Eau Claire WI) W
출원인 / 주소	Supercomputer Systems Limited Partnership (Eau Claire WI 02)
인용정보	피인용 횟수 : 27 인용 특허 : 0

초록 ▼

A distributed architecture for the input/output system for a multiprocessor system provides for equal and democratic access to all shared hardware resources by both the processors and the external interface ports of the multiprocessor system. This allows one or more input/output concentrators attached to the external interface ports to have complete access to all of the shared hardware resources across the multiprocessor system without requiring processor intervention. The distributed input/output system provides for communication of data and control information between a set of common shared hardware resources and a set of external data sources. The result is a highly parallel multiprocessor system that has multiple parallel high performance input/output ports capable of operating in a distributed fashion. The distributed architecture also permits both processors and external interface ports to access all of the shared data structures associated with the operating system that contain the input/output control information.

대표청구항 ▼

A cluster channel interface mechanism for a distributed input/output system of a highly parallel multiprocessor system having a plurality of processors tightly coupled to a set of common shared hardware resources, the distributed input/output system having a plurality of external interface ports which are directly connected to the set of common shared hardware resources, the shared hardware resources including a main memory, a plurality of global registers and an interrupt mechanism, the shared hardware resources having a plurality of operating system shared resources which are stored in the main memory and the global registers and which contain selected information for controlling the operation of the multiprocessor system, the cluster channel interface mechanism comprising: cluster port means operably connected to one of the external interface ports for sending and receiving data and control information between the cluster channel interface mechanism and the set of hardware shared resources; secondary port means operably connected to a secondary memory system for sending and receiving data information between the cluster channel interface mechanism and the secondary memory system; secondary memory transfer controller means operably connected to the secondary port means and the cluster port means for sending and receiving control information related to the secondary memory system and for controlling the transfer of data information between the secondary memory system and the main memory; a plurality of concentrator interface port means, each concentrator interface port means operably connected to a unique channel adapter that is connected to a peripheral controller by a standard channel interface, each concentrator interface port means for sending and receiving control and data information between the cluster channel interface mechanism and the perhipheral controller by the unique channel adapter and the standard channel interface; and switch means operably connected to the cluster port means, the secondary port means and each of the plurality of concentrator interface port means for selectively connecting the cluster port means with the secondary port means or the cluster port means with a selected one of the concentrator interface port means in response to a request to send or receive control and data information between the set of hardware shared resources and the secondary memory system or between the set of hardware shared resources and a selected one of the peripheral controllers, respectively.

이 특허를 인용한 특허 (27) 인용/피인용 타임라인 분석

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Kirn Larry Joseph ; Merritt John ; Lowe Gary K., Method and system for sharing a hardware resource.
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Levin Vladimir K.,RUX ; Karatanov Vjacheslav V.,RUX ; Jalin Valerii V.,RUX ; Titov Alexandr,RUX ; Agejev Vjacheslav M.,RUX ; Patrikeev Andrei,RUX ; Jablonsky Sergei V.,RUX ; Korneev Victor V.,RUX ; M, Method for deadlock-free message passing in MIMD systems using routers and buffers.
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Musoll, Enrique; Nemirovsky, Mario; Huynh, Jeffrey, Packet processor that generates packet-start offsets to immediately store incoming streamed packets using parallel, staggered round-robin arbitration to interleaved banks of memory.
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Miller Steven C. ; Tornes James E., Packetized data transmissions in a switched router architecture.
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Miller,Steven C.; Tornes,James E., Packetized data transmissions in a switched router architecture.
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Mallick Soummya ; McDonald Robert G. ; Swarthout Edward L., Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution.
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Singh, Ravi P.; Roth, Charles P.; Kolagotla, Ravi; Revilla, Juan G., Processor reset and instruction fetches.
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VanHuben Gary Alan ; Blake Michael A. ; Mak Pak-kin, SMP clusters with remote resource managers for distributing work to other clusters while reducing bus traffic to a minimum.
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Bertone James F. ; DiPlacido ; Jr. Bruno ; Joyce Thomas F ; Massucci Martin ; McNally Lance T. ; Murray ; Jr. Thomas L. ; Nibby ; Jr. Chester M. ; Pence Michelle A. ; Sanfacon Marc ; Shen Jian-Kuo ; , Symmetric multiprocessing system with unified environment and distributed system functions.
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Wu William S. ; Rasmussen Norman J. ; Marisetty Suresh K. ; Nizar Puthiya K., Symmetric multiprocessing system with unified environment and distributed system functions.
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Schiffleger Alan J., System and method for distributed multiprocessor communications.
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Griglock, Mark Anthony; Huyck, Patrick John; Ishee, Sidney Slay; Gleason, James Anthony; Erich, Richard Andrew; Aamold, Mathew Lowell, System and method for time variant scheduling of affinity groups comprising processor core and address spaces on a synchronized multicore processor.
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Hansen Dennis D., System for interfacing host computer to multiple peripheral devices using daisy-chainable bus and federated computationa.
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Howlett, Warren K.; Lyles, Christopher L., Systems and methods of accessing common registers in a multi-core processor.
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Griglock, Mark Anthony; Huyck, Patrick John; Ishee, Sidney Slay; Gleason, James Anthony; Erich, Richard Andrew; Aamold, Mathew Lowell, Time-variant scheduling of affinity groups on a multi-core processor.
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Ooe Kazuichi,JPX ; Inano Satoshi,JPX, disk access apparatus for performing a stride processing of data.
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[미국특허] Distributed architecture for input/output for a multiprocessor system 원문보기

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