초록 ▼

A process independent digital clock shaping network is described for generating an internal clock signal having preset high state (Ton) and low state (Toff) intervals per cycle from a received clock signal having a substantially constant period but variable Ton and Toff intervals per cycle. The shap

A process independent digital clock shaping network is described for generating an internal clock signal having preset high state (Ton) and low state (Toff) intervals per cycle from a received clock signal having a substantially constant period but variable Ton and Toff intervals per cycle. The shaping network utilizes a set/reset latch to output the desired clock signal. The set input to the latch receives a set pulse generated at the beginning of each cycle of the received clock signal and the reset input to the latch receives a reset pulse generated by control logic circuitry. The logic circuitry uses the frequency of the received clock signal to generate a reset pulse at the appropriate time for gating of the latch to produce an output clock signal having the desired Ton and Toff intervals per cycle.

대표청구항 ▼

A digital clock signal shaping network, said signal shaping network receiving an input clock signal having a substantially constant period and a variable Ton/Toff ratio per cycle and outputting in response thereto a clock signal having a preset Ton/Toff ratio per cycle, said clock signal shaping net

A digital clock signal shaping network, said signal shaping network receiving an input clock signal having a substantially constant period and a variable Ton/Toff ratio per cycle and outputting in response thereto a clock signal having a preset Ton/Toff ratio per cycle, said clock signal shaping network comprising: a delay circuit having an input coupled to receive said input clock signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a corresponding delay signal as said input clock signal propagates through said delay circuit; a plurality of pulse generators, each of said pulse generators being coupled to receive a respective one of said delay circuit delay signals and output in response thereto a pulse signal, each of said pulse signals having a duration substantially less than the period of said input clock signal, said pulse signals being sequentially output from said pulse generators; a set/reset output latch for producing said clock signal of preset Ton/Toff ratio per cycle, a set input to said output latch being coupled to receive the first pulse signal of said sequential pulse signals output from said plurality of pulse generators, said latch responding to receipt of said first pulse signal by initiating output of a clock signal cycle; and a reset logic circuit coupled to receive as inputs said input clock signal and said pulse signals output from said plurality of pulse generators, said reset logic circuit including means for generating therefrom a reset signal for output to a reset input to said set/reset output latch, said reset signal being timed to produce said preset Ton/Toff ratio per cycle for said outputted clock signal.