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Field programmable gate array 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/173
  • H01L-025/00
출원번호 US-0817697 (1992-01-07)
발명자 / 주소
  • Ebeling William H. C. (Seattle WA) Borriello Gaetano (Seattle WA)
출원인 / 주소
  • Washington Research Foundation (Seattle WA 02)
인용정보 피인용 횟수 : 385  인용 특허 : 0

초록 ▼

A field programmable gate array (FPGA) comprising routing and logic blocks (RLBs) and segmented routing channels is disclosed. Each RLB is configurable to perform both logic functions and routing functions. A plurality of forwardly propagating RLBs (FPRLBs) and a plurality of backwardly propagating

대표청구항 ▼

A field programmable gate array comprising: (a) a plurality of forwardly propagating routing and logic blocks (FPRLBs), each of said FPRLBs having means for receiving a plurality of input signals and a plurality of output signals; and (b) a plurality of backwardly propagating routing and logic block

이 특허를 인용한 특허 (385)

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  159. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Hutton,Michael; Maruri,Victor; Patel,Rakesh; Kazarian,Peter J.; Leaver,Andrew; Mendel,David W.; Park,Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.
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  160. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Maruri,Victor; Patel,Rakesh, Interconnection and input/output resources for programmable logic integrated circuit devices.
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  161. Tony Ngai ; Bruce Pedersen ; Sergey Shumarayev ; James Schleicher ; Wei-Jen Huang ; Michael Hutton ; Victor Maruri ; Rakesh Patel ; Peter J. Kazarian ; Andrew Leaver ; David W. Mendel ; Ji, Interconnection and input/output resources for programmable logic integrated circuit devices.
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  162. Pani,Peter M.; Ting,Benjamin S., Interconnection fabric using switching networks in hierarchy.
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  163. Lee Fung Fung, Interleaved interconnect for programmable logic array devices.
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  164. Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
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  165. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
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  166. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
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  167. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
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  168. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
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  169. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
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  170. Conn, Robert O., Large substrate structural vias.
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  171. Conn, Robert O., Local defect memories on semiconductor substrates in a stack computer.
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  172. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  173. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  174. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  175. Pedersen Bruce B., Logic cell for programmable logic devices.
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  176. Wilson Stanley ; Chan King W. ; Frappier Mark, Logic function module for field programmable array.
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  177. Galbraith Douglas C. (Fremont CA) El Gamal Abbas (Palo Alto CA) Greene Jonathan W. (Palo Alto CA), Logic module for a programmable logic device.
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  178. Galbraith Douglas C. ; El Gamal Abbas ; Greene Jonathan W., Logic module with configurable combinational and sequential blocks.
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  179. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Wang Bonnie I., Logic region resources for programmable logic devices.
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  180. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
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  181. Langhammer, Martin, Matrix decomposition in an integrated circuit device.
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  182. Kurtz, Brian L., Matrix operations in an integrated circuit device.
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  183. Langhammer, Martin, Matrix operations in an integrated circuit device.
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  184. Gaide, Brian C.; Young, Steven P., Merging data streams in a self-timed programmable integrated circuit.
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  185. Chan, Richard, Method and apparatus for a flexible chargepump scheme for field-programmable gate arrays.
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  186. McCollum, John, Method and apparatus for bootstrapping a programmable antifuse circuit.
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  187. Jones Christopher W., Method and apparatus for implementing an internal tri-state bus within a programmable logic circuit.
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  188. Stansfield, Anthony; Marshall, Alan David; Vuillemin, Jean, Method and apparatus for providing instruction streams to a processing device.
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  189. Pani Peter M. ; Ting Benjamin S., Method and apparatus for universal program controlled bus.
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  190. Pani Peter M. ; Ting Benjamin S., Method and apparatus for universal program controlled bus architecture.
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  191. Pani, Peter M.; Ting, Benjamin S., Method and apparatus for universal program controlled bus architecture.
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  192. Pani, Peter M.; Ting, Benjamin S., Method and apparatus for universal program controlled bus architecture.
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  193. Pani, Peter M.; Ting, Benjamin S., Method and apparatus for universal program controlled bus architecture.
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  194. Pani, Peter M.; Ting, Benjamin S., Method and apparatus for universal program controlled bus architecture.
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  195. Pani,Peter M.; Ting,Benjamin S., Method and apparatus for universal program controlled bus architecture.
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  196. Stansfield, Anthony; Marshall, Alan David; Vuillemin, Jean, Method and apparatus for varying instruction streams provided to a processing device using masks.
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  197. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
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  198. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
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  199. Mauer, Volker; Demirsoy, Suleyman Sirri, Method for configuring a finite impulse response filter in a programmable logic device.
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  200. Patterson Cameron D. ; Dellinger Eric F. ; Hwang L. James ; Mitra Sujoy ; Mohan Sundararajarao ; Wittig Ralph D., Method for constraining circuit element positions in structured layouts.
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  201. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
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  202. Vorbach, Martin, Method for debugging reconfigurable architectures.
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  203. Vorbach, Martin, Method for debugging reconfigurable architectures.
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  204. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
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  205. Vorbach,Martin, Method for debugging reconfigurable architectures.
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  206. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.
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  207. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.
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  208. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
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  209. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
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  210. L. James Hwang ; Cameron D. Patterson, Method for remapping logic modules to resources of a programmable gate array.
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  211. Mohan Sundararajarao ; Dellinger Eric F. ; Hwang L. James ; Mitra Sujoy ; Wittig Ralph D., Method for specifying routing in a logic module by direct module communication.
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  212. L. James Hwang ; Cameron D. Patterson ; Sujoy Mitra, Method for structured layout in a hardware description language.
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  213. Vorbach Martin,DEX ; Munch Robert,DEX, Method for the automatic address generation of modules within clusters comprised of a plurality of these modules.
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  214. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
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  215. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
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  216. Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).
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  217. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
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  218. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.
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  219. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.
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  220. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  221. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  222. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  223. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  224. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.
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  225. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
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  226. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
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  227. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.
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  228. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  229. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  230. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  231. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.
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  232. Vorbach, Martin, Methods and devices for treating and/or processing data.
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  233. Young, Steven P.; Tanikella, Ramakrishna K., Methods of initializing routing structures in integrated circuits.
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  234. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
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  235. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
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  236. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
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  237. Kundu, Arunangshu; Narayanan, Venkatesh; McCollum, John; Plants, William C., Multi-level routing architecture in a field programmable gate array having transmitters and receivers.
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  238. Kundu,Arunangshu; Narayanan,Venkatesh; McCollum,John; Plants,William C., Multi-level routing architecture in a field programmable gate array having transmitters and receivers.
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  239. Alexanian, Suren A., Multi-level semiconductor memory architecture and method of forming the same.
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  240. Alexanian,Suren A., Multi-level semiconductor memory architecture and method of forming the same.
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  241. Gaide, Brian C.; Young, Steven P., Multi-mode circuit in a self-timed integrated circuit.
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  242. Langhammer, Martin, Multi-operand floating point operations in a programmable integrated circuit device.
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  243. Plants William C. ; Bakker Gregory W., Multiple logic family compatible output driver.
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  244. Langhammer, Martin, Multiple-precision processing block in a programmable integrated circuit device.
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  245. Young, Steven P.; Gaide, Brian C., Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same.
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  246. Young, Steven P., Multiplier circuits with optional shift function.
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  247. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y., Multiplier-accumulator circuitry and methods.
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  248. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
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  249. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
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  250. Sample Stephen P. ; Butts Michael R., Optimized emulation and prototyping architecture.
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  251. Sample, Stephen P.; Butts, Michael R., Optimized emulation and prototyping architecture.
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  252. Gaide, Brian C.; Young, Steven P., Output structure with cascaded control signals for logic blocks in integrated circuits, and methods of using the same.
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  253. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., PCI-compatible programmable logic devices.
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  254. Cliff Richard G. ; Huang Joseph ; Sung Chiakang ; Wang Bonnie I., PCI-compatible programmable logic devices.
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  255. Cliff, Richard G.; Heile, Francis B.; Huang, Joseph; Mendel, David W.; Pendersen, Bruce B.; Sung, Chiakang; Veenstra, Kerry; Wang, Bonnie I., PCI-compatible programmable logic devices.
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  256. Cliff,Richard G; Heile,Francis B; Huang,Joseph; Mendel,David W; Pedersen,Bruce B; Sung,Chiakang; Veenstra,Kerry; Wang,Bonnie I, PCI-compatible programmable logic devices.
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  257. Sun, Shin Nan; Wong, Wayne W., Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA.
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  258. Sun, Shin-Nan; Wong, Wayne W., Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA.
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  259. Sun,Shin Nan; Wong,Wayne W., Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA.
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  260. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
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  261. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
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  262. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
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  263. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.
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  264. Mauer, Volker; Langhammer, Martin, Pipelined systolic finite impulse response filter.
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  265. Young, Steven P., Pipelined unidirectional programmable interconnect in an integrated circuit.
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  266. Langhammer, Martin, Polynomial calculations optimized for programmable integrated circuit device structures.
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  267. Conn, Robert O., Preventing breakage of long metal signal conductors on semiconductor substrates.
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  268. Conn, Robert O., Preventing breakage of long metal signal conductors on semiconductor substrates.
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  269. Vorbach Martin,DEX ; Munch Robert,DEX, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like).
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  270. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
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  271. Martin Vorbach DE; Robert Munch DE, Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like).
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  272. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
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  273. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
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  274. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
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  275. Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
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  276. Langhammer, Martin, Programmable device using fixed and configurable logic to implement floating-point rounding.
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  277. Langhammer, Martin, Programmable device using fixed and configurable logic to implement recursive trees.
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  278. Mauer, Volker; Langhammer, Martin, Programmable device with specialized multiplier blocks.
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  279. Kaviani, Alireza S., Programmable integrated circuit and method of asynchronously routing data in a circuit block of an integrated circuit.
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  280. Kaviani, Alireza S., Programmable integrated circuit and method of asynchronously routing data in an integrated circuit.
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  281. Gamal Abbas El ; El-Avat Khaled A. ; Mohsen Amr, Programmable interconnect architecture.
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  282. Trimberger, Stephen M., Programmable interconnect element and method of implementing a programmable interconnect element.
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  283. Leong William W. (San Francisco CA) Cliff Richard G. (Milpitas CA) McClintock Cameron (Mountain View CA), Programmable logic array device with grouped logic regions and three types of conductors.
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  284. Mendel David W., Programmable logic array devices with enhanced interconnectivity between adjacent logic regions.
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  285. Mendel David W., Programmable logic array devices with enhanced interconnectivity between adjacent logic regions.
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  286. McClintock Cameron ; Leong William ; Cliff Richard G. ; Ahanin Bahram, Programmable logic array devices with interconnect lines of various lengths.
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  287. McClintock Cameron ; Leong William ; Cliff Richard G. ; Ahanin Bahram, Programmable logic array devices with interconnect lines of various lengths.
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  288. McClintock Cameron ; Leong William ; Cliff Richard G. ; Ahanin Bahram, Programmable logic array devices with interconnect lines of various lengths.
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  289. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lane Christopher F. ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Ngo Ninh D. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ;, Programmable logic array integrated circuit architectures.
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  290. Cliff Richard G. ; Heile Francis B. ; Sung Chiakang ; Wang Bonnie I. ; Pedersen Bruce B., Programmable logic array integrated circuit architectures.
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  291. Richard G. Cliff ; Francis B. Heile ; Joseph Huang ; Christopher F. Lane ; Fung Fung Lee ; Cameron McClintock ; David W. Mendel ; Ninh D. Ngo ; Bruce B. Pedersen ; Srinivas T. Reddy ; Chiak, Programmable logic array integrated circuit architectures.
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  292. Cliff Richard G. (Milpitas CA) Reddy Srinivas T. (Santa Clara CA) Raman Rina (Fremont CA) Cope L. Todd (San Jose CA) Huang Joseph (San Jose CA) Pedersen Bruce B. (San Jose CA), Programmable logic array integrated circuit devices.
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  293. Cliff Richard G. ; Reddy Srinivas T. ; Jefferson David E. ; Raman Rina ; Cope L. Todd ; Lane Christopher F. ; Huang Joseph ; Heile Francis B. ; Pedersen Bruce B. ; Mendel David W. ; Lytle Craig S. ; , Programmable logic array integrated circuit devices.
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  294. Cliff Richard G. ; Reddy Srinivas T. ; Raman Rina ; Cope L. Todd ; Huang Joseph ; Pedersen Bruce B., Programmable logic array integrated circuit devices.
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  295. Cliff Richard G. ; Reddy Srinivas T. ; Raman Rina ; Cope L. Todd ; Huang Joseph ; Pedersen Bruce B., Programmable logic array integrated circuit devices.
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  296. Cliff, Richard G.; Reddy, Srinivas T.; Jefferson, David Edward; Raman, Rina; Cope, L. Todd; Lane, Christopher F.; Huang, Joseph; Heile, Francis B.; Pedersen, Bruce B.; Mendel, David Wolk; Lytle, Crai, Programmable logic array integrated circuit devices.
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  297. Richard G. Cliff ; Srinivas T. Reddy ; David Edward Jefferson ; Rina Raman ; L. Todd Cope ; Christopher F. Lane ; Joseph Huang ; Francis B. Heile ; Bruce B. Pedersen ; David Wolk Mendel ; C, Programmable logic array integrated circuit devices.
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  298. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lane Christopher F. ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Ngo Ninh D. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ;, Programmable logic array integrated circuit devices with interleaved logic array blocks.
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  299. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., Programmable logic array integrated circuit devices with interleaved logic array blocks.
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  300. Reddy Srinivas T. (Santa Clara CA) Sung Chiakang (Milpitas CA) Wang Bonnie I-Keh (Cupertino CA), Programmable logic array integrated circuits with improved interconnection conductor utilization.
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  301. Leong William (San Francisco CA) McClintock Cameron (Mountain View CA) Cliff Richard G. (Milpitas CA), Programmable logic array integrated circuits with interconnection conductors of overlapping extent.
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  302. Cliff Richard G. ; Reddy Srinivas T. ; Jefferson David E. ; Raman Rina ; Cope L. Todd ; Lane Christopher F. ; Huang Joseph ; Heile Francis B. ; Pedersen Bruce B. ; Mendel David W. ; Lytle Craig S. ; , Programmable logic array intergrated circuit devices.
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  303. Jones Gareth James,GBX ; Work Gordon Stirling,GBX, Programmable logic array with a hierarchical routing resource.
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  304. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., Programmable logic device architectures.
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  305. Jefferson, David E.; McClintock, Cameron; Schleicher, James; Lee, Andy L.; Mejia, Manuel; Pedersen, Bruce B.; Lane, Christopher F.; Cliff, Richard G.; Reddy, Srinivas T., Programmable logic device architectures with super-regions having logic regions and a memory region.
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  306. David E. Jefferson ; Cameron McClintock ; James Schleicher ; Andy L. Lee ; Manuel Mejia ; Bruce B. Pederson ; Christopher F. Lane ; Richard G. Cliff ; Srinivas T. Reddy, Programmable logic device architectures with super-regions having logic regions and memory region.
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  307. Lee Andy L. ; Cliff Richard G. ; Jefferson David ; McClintock Cameron ; Altaf Kurosu R., Programmable logic device with enhanced multiplexing capabilities in interconnect resources.
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  308. Lee Andy L. ; Cliff Richard G. ; Jefferson David ; McClintock Cameron ; Altaf Kurosu R., Programmable logic device with enhanced multiplexing capabilities in interconnect resources.
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  309. Reddy Srinivas T. ; Cliff Richard G. ; Lane Christopher F. ; Zaveri Ketan H. ; Mejia Manuel M. ; Jefferson David ; Pedersen Bruce B. ; Lee Andy L., Programmable logic device with hierarchical interconnection resources.
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  310. Reddy Srinivas T. ; Cliff Richard G. ; Lane Christopher F. ; Zaveri Ketan H. ; Mejia Manuel M. ; Jefferson David ; Pedersen Bruce B. ; Lee Andy L., Programmable logic device with hierarchical interconnection resources.
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  311. Reddy, Srinivas T.; Cliff, Richard G.; Lane, Christopher F.; Zaveri, Ketan H.; Mejia, Manuel M.; Jefferson, David; Pedersen, Bruce B.; Lee, Andy L., Programmable logic device with hierarchical interconnection resources.
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