[특허]Configuration of SRAMS as logical FIFOS for transmit and receive of packet data

Configuration of SRAMS as logical FIFOS for transmit and receive of packet data 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H04J-003/02 H04J-003/24
출원번호	US-0529363 (1990-05-29)
발명자 / 주소	Firoozmand Farzin (Cupertino CA)
출원인 / 주소	Advanced Micro Devices, Inc. (Sunnyvale CA 02)
인용정보	피인용 횟수 : 63 인용 특허 : 0

초록 ▼

Data arranged in packets are transferred between a system memory and a network bus through a SRAM configured by software pointers as first in-first out memories for transmitting (transmit FIFO) and for receiving (receive FIFO). The packets of data stored in the transmit and receive FIFOs are demarked from each other and classified by tag and status bits at the end of the last word of each packet. Data to be transmitted on the network bus is transferred from the system memory to the transmit FIFO, and data received from the network is stored in the receive FIFO. To maximize data throughput, when either at least a predetermined amount of data or a complete packet is stored in the transmit FIFO, the data is transmitted to the network while data is being received from the system memory. When at least a predetermined amount of data is stored in the receive FIFO, data is transferred to the system memory while network data is incoming from the network. One application of the invention is in a Fiber Distributed Data Interface (FDDI).

대표청구항 ▼

For a Fiber Distributed Data Interface (FDDI) network having a plurality of processors, each including a system memory means for storing frames of data arranged in queues and having a plurality of different transmit priorities, and an optical medium forming a digital data communication path among said processors, a network controller, comprising: first means implementing a timed token data protocol for accessing said optical medium; a random access memory forming a buffer memory; and second means for configuring in said random access memory a plurality of logical FIFOs for storing therein said queued frames of data having respectively said plurality of different transmit priorities; means for controlling flow of said framed data to corresponding logical FIFOs in said buffer memory, said framed data flow controlling means including first means for controlling flow of said framed data, one queue at a time in order of priority, from said system memory means to corresponding logical FIFOs in said buffer memory, and second means for transmitting said framed data, stored in said logical FIFOs to said medium while data is incoming from said system memory means to said FIFOs in said buffer memory; wherein each said logical FIFO is defined by START and END pointers and including a READ pointer and a WRITE pointer respectively for reading data to and writing data from said logical FIFO and a SHADOW WRITE pointer pointing to the end of a full frame stored in said logical FIFO, and wherein said data flow controlling means includes means for detecting when said SHADOW WRITE pointer exceeds said READ pointer.

이 특허를 인용한 특허 (63)

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Configuration of SRAMS as logical FIFOS for transmit and receive of packet data 원문보기

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Configuration of SRAMS as logical FIFOS for transmit and receive of packet data 원문보기

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