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Integrated circuit device having an ic chip mounted on the wiring substrate and having suitable mutual connections betwe 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-039/02
  • H01L-023/48
  • H01L-029/46
출원번호 US-0755652 (1991-09-06)
우선권정보 JP-0236958 (1990-09-10)
발명자 / 주소
  • Nakanishi Keiichirou (Kokubunji JPX) Yamada Minoru (Hanno JPX) Saitoh Tatsuya (Kokubunji JPX) Yamamoto Kazumichi (Kokubunji JPX)
출원인 / 주소
  • Hitachi, Ltd. (Tokyo JPX 03)
인용정보 피인용 횟수 : 103  인용 특허 : 0

초록 ▼

This invention discloses an integrated circuit device including an integrated circuit chip having logic circuits formed therein and a wiring substrate for mounting thereon the integrated circuit chip. The wiring substrate has signal wirings for connecting mutually input terminals and output terminal

대표청구항 ▼

An integrated circuit device comprising: an integrated circuit chip having a plurality of logic circuits formed therein; first signal wirings disposed inside said integrated circuit chip; output terminals for providing output signals of said logic circuits from said integrated circuit chip; input te

이 특허를 인용한 특허 (103)

  1. Lin, Mou-Shiung, Capacitor for high performance system-on-chip using post passivation device.
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  2. Mou-Shiung Lin TW, Capacitor for high performance system-on-chip using post passivation process structure.
    상세보기
  3. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
    상세보기
  4. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
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  5. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
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  6. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
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  7. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
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  8. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.
    상세보기
  9. Thomas H. DiStefano ; John W. Smith, Chip with internal signal routing in external element.
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  10. Desbiens, Donald J.; Polhemus, Gary D.; Carroll, Robert T., Electrical connectivity for circuit applications.
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  11. Polhemus, Gary D.; Carroll, Robert T.; Desbiens, Donald J., Electrical connectivity for circuit applications.
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  12. Carroll, Robert T., Electrical connectivity of die to a host substrate.
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  13. Carroll, Robert T., Electrical connectivity of die to a host substrate.
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  14. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
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  15. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
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  16. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
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  17. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
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  18. Lin, Mou Shiung, High performance system-on-chip passive device using post passivation process.
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  19. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
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  20. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
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  21. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
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  22. Lin,Mou Shiung, High performance system-on-chip using post passivation process.
    상세보기
  23. Lin,Mou Shiung, High performance system-on-chip using post passivation process.
    상세보기
  24. Mou-Shiung Lin TW, Inductor structure for high performance system-on-chip using post passivation process.
    상세보기
  25. Ahn, Byung Hoon; Kim, OhSug, Integrated circuit package system with down-set die pad and method of manufacture thereof.
    상세보기
  26. Erickson Brian D., Integrated circuit packaged for receiving another integrated circuit.
    상세보기
  27. Suzuki Rieko,JPX ; Saida Kiyoshi,JPX ; Itazu Kazushige,JPX ; Fujine Eiji,JPX ; Kamiya Yoshihiro,JPX ; Uchida Yoshitaka,JPX ; Murakami Takako,JPX ; Tsuyuki Teruhisa,JPX ; Kawazoe Kazunori,JPX ; Shimaz, Manufacturing method and apparatus of a semiconductor integrated circuit device.
    상세보기
  28. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Method for fabricating circuitry component.
    상세보기
  29. Lin Mou-Shiung,TWX, Method for forming high performance system-on-chip using post passivation process.
    상세보기
  30. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
    상세보기
  31. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
    상세보기
  32. Norman,Richard S.; Chamberlain,David, Microelectronic complex having clustered conductive members.
    상세보기
  33. DiStefano, Thomas H.; Smith, John W., Off-chip signal routing between multiply-connected on-chip electronic elements via external multiconductor transmission line on a dielectric element.
    상세보기
  34. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
    상세보기
  35. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
    상세보기
  36. Lin,Mou Shiung; Chou,Chien Kang; Chou,Chiu Ming, Post passivation interconnection process and structures.
    상세보기
  37. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection process and structures.
    상세보기
  38. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chip.
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  39. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  40. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  41. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  42. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  43. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  44. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
    상세보기
  45. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
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  46. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
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  47. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
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  48. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
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  49. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
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  50. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chips.
    상세보기
  51. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
    상세보기
  52. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
    상세보기
  53. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
    상세보기
  54. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
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  55. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  56. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  57. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  58. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  59. Mou-Shiung Lin TW; Jin-Yuan Lee TW, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  60. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
    상세보기
  61. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
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  62. Lin, Mou-Shiung; Lei, Ming-Ta; Lee, Jin-Yuan; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
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  63. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
    상세보기
  64. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
    상세보기
  65. Mou-Shiung Lin TW, Resistor for high performance system-on-chip using post passivation process.
    상세보기
  66. Yamada, Naoto; Kobayashi, Norihiro, Semiconductor device having a matrix array of contacts and a fabrication process thereof.
    상세보기
  67. Yamada, Naoto; Kobayashi, Norihiro, Semiconductor device having a matrix array of contacts and a fabrication process thereof.
    상세보기
  68. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  69. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  70. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  71. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  72. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  73. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  74. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  75. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  76. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  77. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
    상세보기
  78. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  79. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
    상세보기
  80. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  81. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  82. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  83. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  84. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  85. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  86. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  87. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  88. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  89. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  90. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  91. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  92. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  93. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  94. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  95. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  96. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  97. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  98. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  99. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  100. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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  101. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
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  102. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
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  103. Lin, Mou-Shiung; Wei, Gu-Yeon, Voltage regulator integrated with semiconductor chip.
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