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| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0437858 (1989-11-17) |
| 발명자 / 주소 |
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| 출원인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 345 인용 특허 : 0 |
There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memor
There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip. Each processor can operate to execute the same instruction at the same time (SIMD mode) or different instructions at the same time (MIMD mode).
A multi-processor system operable in either a single instruction multiple data (SIMD) mode or in a multiple instruction multiple data (MIMD) mode comprising: a SIMD/MIMD mode register storing therein an indication of either the single instruction multiple data (SIMD) mode or the multiple instruction
A multi-processor system operable in either a single instruction multiple data (SIMD) mode or in a multiple instruction multiple data (MIMD) mode comprising: a SIMD/MIMD mode register storing therein an indication of either the single instruction multiple data (SIMD) mode or the multiple instruction multiple data (MIMD) mode; a plurality of processors, each processors having a data port and an instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port; a plurality of memories, said plurality of memories including at least one data memory corresponding to each of said processors and an instruction memory corresponding to each of said processors; a switch matrix connected to said SIMD/MIMD mode register, to each of said plurality of processors and each of said plurality of memories, said switch matrix including a set of first links connected to said memories, a set of second links connected to said data ports of said processors, a third link having a plurality of sections equal in number to the number of said processors, each section connected to said instruction port of a corresponding one of said processors, a plurality of buffers disposed between adjacent sections of said third link connecting said adjacent sections of said third link when said SIMD/MIMD mode register indicates the single instruction multiple data (SIMD) mode, and splitting said adjacent sections of said third link when said SIMD/MIMD mode register indicates the multiple instruction multiple data (MIMD) mode, and a plurality of crosspoints disposed at intersections between said first links and said second links and at intersections between said first links and said sections of said third link, said crosspoints individually operating to connect said first and second links permitting said data port of a processors to access a memory, and to connect said first links and said third link permitting said instruction port of a processor to receive an instruction from an instruction memory, said plurality of crosspoints including a first crosspoint disposed at the intersection of said section of said third link connected to said instruction port of a predetermined first processor and said first link connected to said corresponding instruction memory which is always enabled to permit connection, said plurality of crosspoints including a set of second crosspoints disposed at the intersection of said section of said first link connected to said instruction port of processors other than said predetermined first processor and said respective first link connected to said corresponding instruction memories which are disabled to prohibit connection when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode and enabled to permit connection when said SIMD/MIMD register indicates the multiple instruction multiple data (MIMD) mode; whereby said instruction port of each processor is connected to said instruction memory corresponding to said predetermined first processor in the single instruction multiple data (SIMD) mode via said first crosspoint, said sections of said third link and said buffers, and said instruction port of each processor is connected to said corresponding instruction memory in the multiple instruction multiple data (MIMD) mode via said corresponding second crosspoint and said corresponding section of said third link.
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