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Method of making an adaptive configurable gate array 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/80
  • H01L-021/304
출원번호 US-0651068 (1991-02-04)
발명자 / 주소
  • Anderson James M. (Huntington Beach CA) Coulson Andrew R. (Santa Monica CA) Demaioribus Vincent J. (Redondo Beach CA) Nicholas Henry T. (Redondo Beach CA)
출원인 / 주소
  • TRW Inc. (Redondo Beach CA 02)
인용정보 피인용 횟수 : 127  인용 특허 : 0

초록 ▼

A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application s

대표청구항 ▼

The process of forming an ASIC chip which comprises the steps of: forming a configurable gate array on a semiconductor wafer, said array containing a plurality of transistors arranged in rows and columns; personalizing said array to define at least one application specific integrated circuit located

이 특허를 인용한 특허 (127)

  1. Or-Bach, Zvi; Wurman, Ze'ev, 3D integrated circuit with logic.
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  7. Or-Bach, Zvi; Cronquist, Brian; Sekar, Deepak, 3D semiconductor device and structure.
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  8. Or-Bach, Zvi; Cronquist, Brian; Sekar, Deepak, 3D semiconductor device and structure.
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  9. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian, 3D semiconductor device and structure.
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  10. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk, 3D semiconductor device and structure.
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  11. Sekar, Deepak; Or-Bach, Zvi; Cronquist, Brian, 3D semiconductor device and structure.
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  12. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Beinglass, Israel; Wurman, Ze'ev; Lim, Paul, 3D semiconductor device and structure with back-bias.
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  13. Or-Bach, Zvi; Wurman, Ze'ev, 3D semiconductor device including field repairable logics.
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  14. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Wurman, Zeev, 3D semiconductor device, fabrication method and system.
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  15. Or-Bach, Zvi; Widjaja, Yuniarto, 3DIC system with a two stable state memory and back-bias region.
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  16. Or-Bach, Zvi; Wurman, Zeev, Automation for monolithic 3D devices.
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  27. Bansal,Jai P., Method for designing structured ASICS in silicon processes with three unique masking steps.
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  30. Cronquist, Brian; Beinglass, Isreal; de Jong, Jan Lodewijk; Sekar, Deepak C.; Or-Bach, Zvi, Method for fabrication of a semiconductor device and structure.
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  31. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Isreal; de Jong, Jan Lodewijk; Sekar, Deepak C., Method for fabrication of a semiconductor device and structure.
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  32. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian, Method for fabrication of a semiconductor device and structure.
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  33. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk, Method for fabrication of a semiconductor device and structure.
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  35. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk, Method for fabrication of a semiconductor device and structure.
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  36. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Lim, Paul, Method for fabrication of a semiconductor device and structure.
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  39. Or-Bach, Zvi; Sekar, Deepak C.; Cronquist, Brian; Beinglass, Israel; de Jong, Jan Lodewijk, Method for fabrication of configurable systems.
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  40. Nelson,Michael D., Method for storing and shipping programmable ASSP devices.
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  41. Blanchard, Richard A., Method for using a surface geometry for a MOS-gated device in the manufacture of dice having different sizes.
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  43. Bang, Ju-mi, Method of creating photo mask layout, computer readable recording medium storing programmed instructions for executing the method, and mask imaging system.
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  45. Sivilotti Massimo Antonio ; Tanner John Edward ; Luo Jin, Method of fabricating various-sized passivated integrated circuit chips from a borderless gate array.
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  46. Kim, Eunjung; Park, Sohyun; Kim, Bong-Soo; Hwang, Yoosang; Kim, Dong-Wan; Han, Junghoon, Method of forming semiconductor device including edge chip and related device.
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  47. Or-Bach, Zvi; Sekar, Deepak; Cronquist, Brian; Wurman, Ze'ev, Method of forming three dimensional integrated circuit devices using layer transfer technique.
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  48. Or-Bach, Zvi; Widjaja, Yuniarto, Method of maintaining a memory state.
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  49. Pasch Nicholas F. (Pacifica CA), Method of making an integrated circuit chip having an array of logic gates.
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  51. Sekar, Deepak C.; Or-Bach, Zvi, Method of manufacturing a semiconductor device with two monocrystalline layers.
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  52. Or-Bach, Zvi; Cronquist, Brian; Beinglass, Israel; de Jong, J. L.; Sekar, Deepak C.; Lim, Paul, Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer.
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  53. Or-Bach, Zvi; Cronquist, Brian; Sekar, Deepak, Method of processing a semiconductor device.
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  54. Or-Bach, Zvi; Wurman, Zeev, Method to construct a 3D semiconductor device.
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  55. Or-Bach, Zvi; Wurman, Ze'ev, Method to construct systems.
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  58. Boyle, Adrian A.; Meignan, Oonagh, Methods and systems for laser machining a substrate.
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