[특허]Programmable priority arbiter

Programmable priority arbiter 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-013/14
출원번호	US-0828026 (1992-01-30)
발명자 / 주소	O\Connell Anne (Galway IEX) Creedon Tadhg (Galway IEX) Smith Deidre A. (Kildare IEX)
출원인 / 주소	Digital Equipment Corporation (Maynard MA 02)
인용정보	피인용 횟수 : 72 인용 특허 : 0

초록 ▼

The present invention is directed to a programmable logic circuit used as an arbiter to control access to a shared resource, e.g. a system bus, by N devices in a computer system. The programmable arbiter according to the present invention, implements a logic design with sufficient flexibility to accommodate and selectively incorporate features of several different arbitration schemes including a straight priority scheme, a programmable arbitration, and a rotating priority arbitration scheme. In addition to these arbitration schemes, the arbiter of the present invention supports an extended programmable arbitration scheme whereby a device which is requesting access to the shared resource may be granted access to the resource even if it has used up its allocated share of bandwidth if there are no other devices requesting access to the shared resource. Furthermore, bus bandwidth may be allocated to particular device or to a group of devices at a particular priority level. In addition to providing for programmable allocation of bus bandwidth, the arbiter of the present invention permits the number of clock cycles allocated per bus window for one requesting device to be different from the number of clock cycles allocated per bus window for another device. In this manner, the size of the bus window can be designed to accommodate the individual requirements of each device permitting maximization of both the device\s and the system\s overall efficiency.

대표청구항 ▼

A programmable arbiter for granting access to a shared resource among N requestors, comprising: an access control system comprising an access control logic device and a total window counter coupled to the access control logic device, the total window counter storing information on an allocation period for access to the shared resource, the allocation period comprising a preselected number of windows; the access control logic device storing a series of numbers, each number comprising a number of windows per allocation period available for use by a respective one of the N requestors; the access control device adapted for receiving request signals from the N requestors; the access control logic device including a plurality of grant signal outputs, each one of the grant signal outputs corresponding to one of the N requestors; each one of the grant signal outputs adapted for coupling to the corresponding one of the N requestors; and a plurality of counters, each of the counters programmed to store information on a number of clock cycles available for use by a respective one of the N requestors during a window; each one of the counters coupled to a respective one of the grant signal outputs; each of the counters further coupled to the access control device to increment and provide a signal representative of a number of windows used by the corresponding one of the N requestors during the current allocation period when a grant signal is asserted on the respective grant output, and upon counting the number of clock cycles; the access control logic device operating to generate a grant signal on one of the grant signal outputs as a function of the request signals received from the N requestors and the signal representative of the number of windows used received from the plurality of counters; the incrementing of the signal representative of the number of windows used, by the counter corresponding to the grant signal output having the grant signal, providing an indication to the access control device that a next grant signal can be generated.

이 특허를 인용한 특허 (72)

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Sakakibara Tadayuki (Kunitachi JPX) Tanaka Teruo (Hachioji JPX) Kitai Katsuyoshi (Polo Alto CA) Isobe Tadaaki (Hadano JPX) Hashimoto Shigeko (Hadano JPX) Inagami Yasuhiro (Kodaira JPX) Tamaki Yoshiko, Interprocessor priority control system for multivector processor.
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Park, Hee-Chul, Interrupt signal processing circuit for sending interrupt requests to a computer system.
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Bauman Mitchell A. ; Carlin Jerome G. ; Gilbertson Roger L., Memory queue with adjustable priority and conflict detection.
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Chowdhuri, Bhaskar, Method and apparatus for bus arbitration dynamic priority based on waiting period.
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Chowdhuri,Bhaskar, Method and apparatus for bus arbitration dynamic priority based on waiting period.
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Leung Wan L. (Coral Springs FL), Method and apparatus for bus arbitration in a multiple bus information handling system using time slot assignment values.
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Chowdhuri, Bhaskar, Method and apparatus for dynamically granting access of a shared resource among a plurality of requestors.
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Chowdhuri, Bhaskar, Method and apparatus for dynamically granting access of a shared resource among a plurality of requestors.
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Chowdhuri, Bhaskar, Method and apparatus for dynamically granting access of a shared resource among a plurality of requestors.
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Lai, Siaw Kang, Providing a fine-grained arbitration system.
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Tran Cang Ngoc ; Kahle James Allan, Selectable priority bus arbitration scheme.
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Emnett Raymond F., System and method for arbitrating multi-function access to a system bus.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Programmable priority arbiter 원문보기

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Programmable priority arbiter 원문보기

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