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Configurable electrical circuit having configurable logic elements and configurable interconnects 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
출원번호 US-0720275 (1991-06-24)
발명자 / 주소
  • Freeman
  • deceased Ross H. (late of San Jose CA by Dennis Hersey
  • executor)
출원인 / 주소
  • Xilinx, Inc. (San Jose CA 02)
인용정보 피인용 횟수 : 553  인용 특허 : 0

초록

A configurable logic array comprises a plurality of configurable logic elements variably interconnected in response to control signals to perform a selected logic function. Each configurable logic element in the array is in itself capable of performing any one of a plurality of logic functions depen

대표청구항

A programmable circuit comprising: a plurality of logic elements, each logic element having a plurality of input leads and at least one output lead, and having a programming means to cause said logic element to perform a selected logic function; a plurality of input/output ports; a group of inte

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  211. Tony Ngai ; Bruce Pedersen ; Sergey Shumarayev ; James Schleicher ; Wei-Jen Huang ; Michael Hutton ; Victor Maruri ; Rakesh Patel ; Peter J. Kazarian ; Andrew Leaver ; David W. Mendel ; Ji, Interconnection and input/output resources for programmable logic integrated circuit devices.
  212. Pani,Peter M.; Ting,Benjamin S., Interconnection fabric using switching networks in hierarchy.
  213. James Schleicher ; James Park ; Sergey Shumarayev ; Bruce Pedersen ; Tony Ngai ; Wei-Jen Huang ; Victor Maruri ; Rakesh Patel, Interconnection resources for programmable logic integrated circuit devices.
  214. Schleicher, James; Park, James; Shumarayev, Sergey; Pedersen, Bruce; Ngai, Tony; Huang, Wei-Jen; Maruri, Victor; Patel, Rakesh, Interconnection resources for programmable logic integrated circuit devices.
  215. Schleicher, James; Park, James; Shumarayev, Sergey; Pedersen, Bruce; Ngai, Tony; Huang, Wei-Jen; Maruri, Victor; Patel, Rakesh, Interconnection resources for programmable logic integrated circuit devices.
  216. Schleicher, James; Park, James; Shumarayev, Sergey; Pedersen, Bruce; Ngai, Tony; Huang, Wei-Jen; Maruri, Victor; Patel, Rakesh, Interconnection resources for programmable logic integrated circuit devices.
  217. Schleicher,James; Park,Jim; Shumarayev,Sergey; Pederson,Bruce; Ngai,Tony; Huang,Wei Jen; Maruri,Victor; Patel,Rakesh, Interconnection resources for programmable logic integrated circuit devices.
  218. Lee, Andy L., Interconnection switch structures.
  219. Lee Fung Fung, Interleaved interconnect for programmable logic array devices.
  220. Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
  221. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
  222. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  223. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  224. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  225. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  226. Kaviani, Alireza S., Literal sharing method for fast sum-of-products logic.
  227. Kaviani, Alireza S., Literal sharing method for fast sum-of-products logic.
  228. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  229. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  230. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  231. Pedersen Bruce B., Logic cell for programmable logic devices.
  232. Katakura,Hiroshi; Nakashima,Yasuhiko, Logic circuit.
  233. Francis B. Heile, Logic device architecture and method of operation.
  234. Heile Francis B., Logic device architecture and method of operation.
  235. Wei-Jen Huang ; Sergey Shumarayev ; Tony Ngai ; Bruce Pedersen, Logic module circuitry for programmable logic devices.
  236. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Wang Bonnie I., Logic region resources for programmable logic devices.
  237. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
  238. Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.
  239. Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.
  240. Bauer Trevor J., Lookup tables which double as shift registers.
  241. Gould Scott Whitney ; Furtek Frederick Curtis ; Keyser ; III Frank Ray ; Worth Brian A. ; Zittritsch Terrance John, Low skew multiplexer network and programmable array clock/reset application thereof.
  242. Langhammer, Martin, Matrix decomposition in an integrated circuit device.
  243. Kurtz, Brian L., Matrix operations in an integrated circuit device.
  244. Langhammer, Martin, Matrix operations in an integrated circuit device.
  245. Rangasayee Krishna ; Bielby Robert N., Memory cells configurable as CAM or RAM in programmable logic devices.
  246. Rangasayee Krishna ; Bielby Robert N., Memory cells configurable as CAM or RAM in programmable logic devices.
  247. Theron, Conrad A.; St. Pierre, Jr., Donald H., Method and apparatus for changing execution code for a microcontroller on an FPGA interface device.
  248. New Bernard J., Method and apparatus for controlling the partial reconfiguration of a field programmable gate array.
  249. Chapman, Kenneth D., Method and apparatus for de-spreading spread spectrum signals.
  250. Cory,Warren E., Method and apparatus for operating a transceiver in different data rates.
  251. Douglass,Stephen M.; Ansari,Ahmad R., Method and apparatus for processing data with a programmable gate array using fixed and programmable processors.
  252. Trimberger, Stephen M., Method and apparatus for protecting proprietary configuration data for programmable logic devices.
  253. Trimberger,Stephen M., Method and apparatus for protecting proprietary decryption keys for programmable logic devices.
  254. Wang, Man, Method and apparatus for providing a non-volatile programmable transistor.
  255. James Schleicher, Method and apparatus for reducing memory resources in a programmable logic device.
  256. Gan, Andy H., Method and apparatus for routing interconnects to devices with dissimilar pitches.
  257. Ansari,Ahmad R.; Vashi,Mehul R., Method and apparatus for synchronized buses.
  258. Fang, Ying, Method and apparatus for testing an embedded device.
  259. Herron,Nigel G.; Thorne,Eric J.; Wang,Qingqi, Method and apparatus for testing circuitry embedded within a field programmable gate array.
  260. Burnley,Richard P.; Oda,Shizuka; Gan,Andy H., Method and apparatus for timing modeling.
  261. Oda,Shizuka; Burnley,Richard P., Method and apparatus for timing modeling.
  262. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  263. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  264. Schultz David P. ; Hung Lawrence C. ; Goetting F. Erich, Method and structure for configuring FPGAS.
  265. Schultz David P. ; Young Steven P. ; Hung Lawrence C., Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA.
  266. Yin, Robert; Vashi, Mehul R., Method and system for controlling default values of flip-flops in PGA/ASIC-based designs.
  267. Sanchez, Reno L.; Linn, John H., Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC).
  268. Sanchez,Reno L.; Linn,John H., Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC).
  269. Schultz,David P., Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC).
  270. Allegrucci, Jean-Didier, Method and system for interfacing an integrated circuit to synchronous dynamic memory and static memory.
  271. Patrie Robert D. ; Wells Robert W. ; Young Steven P. ; Kingsley Christopher H. ; Chung Daniel ; Conn Robert O., Method and system for measuring signal propagation delays using ring oscillators.
  272. Kingsley Christopher H. ; Patrie Robert D. ; Wells Robert W. ; Conn Robert O., Method and system for measuring signal propagation delays using the duty cycle of a ring oscillator.
  273. Stadler,Laurent, Method for bus mastering for devices resident in configurable system logic.
  274. Conn Robert O., Method for characterizing interconnect timing characteristics.
  275. Conn Robert O., Method for characterizing interconnect timing characteristics using reference ring oscillator circuit.
  276. Mauer, Volker; Demirsoy, Suleyman Sirri, Method for configuring a finite impulse response filter in a programmable logic device.
  277. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
  278. Vorbach, Martin, Method for debugging reconfigurable architectures.
  279. Vorbach, Martin, Method for debugging reconfigurable architectures.
  280. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
  281. Vorbach,Martin, Method for debugging reconfigurable architectures.
  282. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.
  283. McGettigan Edward S. ; Tran Jennifer T. ; Goetting F. Erich, Method for design implementation of routing in an FPGA using placement directives such as local outputs and virtual buffers.
  284. Theron Conrad A. ; Resler Edwin W. ; St. Pierre ; Jr. Donald H., Method for detecting low power on an FPGA interface device.
  285. Young Steven P., Method for generating an FPGA two turn routing structure with lane changing and minimum diffusion area.
  286. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.
  287. Wong, Barry, Method for implementing dynamic burn-in testing using static test signals.
  288. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
  289. St. Pierre ; Jr. Donald H. ; Theron Conrad A., Method for level shifting logic signal voltage levels.
  290. LaBerge Paul A., Method for modifying an integrated circuit.
  291. LaBerge, Paul A., Method for modifying an integrated circuit.
  292. LaBerge,Paul A., Method for modifying an integrated circuit.
  293. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
  294. Tharmalingam,Kumara, Method for programming programmable logic device having specialized functional blocks.
  295. Carmichael Carl H. ; Theron Conrad A. ; St. Pierre ; Jr. Donald H., Method for reconfiguring a field programmable gate array from a host.
  296. Conrad A. Theron ; Donald H. St. Pierre, Jr., Method for resisting an FPGA interface device.
  297. Vorbach Martin,DEX ; Munch Robert,DEX, Method for the automatic address generation of modules within clusters comprised of a plurality of these modules.
  298. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
  299. May,Frank; N?ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
  300. Douglass, Stephen M., Method of designing integrated circuit having both configurable and fixed logic circuitry.
  301. Donald H. St. Pierre, Jr. ; Conrad A. Theron, Method of disguising a USB port connection.
  302. Hart Michael J. ; Look Kevin T. ; Karpovich Yakov, Method of forming multilayer amorphous silicon antifuse.
  303. Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).
  304. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
  305. Elward, John S., Method of monitoring internal voltage and controlling a parameter of an integrated circuit.
  306. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.
  307. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.
  308. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  309. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  310. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  311. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  312. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.
  313. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
  314. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
  315. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.
  316. Trimberger,Stephen M., Methods and circuits for preventing the overwriting of memory frames in programmable logic devices.
  317. Trimberger,Stephen M., Methods and circuits for protecting proprietary configuration data for programmable logic devices.
  318. Trimberger,Stephen M., Methods and circuits for protecting proprietary configuration data for programmable logic devices.
  319. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  320. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  321. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  322. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.
  323. Vorbach, Martin, Methods and devices for treating and/or processing data.
  324. Lee,Andy L.; McClintock,Cameron; Johnson,Brian; Cliff,Richard; Reddy,Srinivas; Lane,Chris; Leventis,Paul; Betz,Vaughn Timothy; Lewis,David, Methods for designing PLD architectures for flexible placement of IP function blocks.
  325. Trimberger, Stephen M., Methods for implementing circuits in programmable logic devices to minimize the effects of single event upsets.
  326. Nazarian Hagop A. ; Douglass Stephen M. ; Graf W. Alfred ; Raza S. Babar ; Rajan Sundar ; Borzin Shiva Sorooshian ; Neuman Darren, Methods for maximizing routability in a programmable interconnect matrix having less than full connectability.
  327. Nazarian Hagop A. ; Douglass Stephen M. ; Graf W. Alfred ; Raza S. Babar ; Rajan Sundar ; Borzin Shiva Sorooshian ; Newman Darren, Methods for maximizing routability in a programmable interconnect matrix having less than full connectability.
  328. James L. Burnham ; Gary R. Lawman ; Joseph D. Linoff, Methods to securely configure an FPGA to accept selected macros.
  329. Burnham James L., Methods to securely configure an FPGA using encrypted macros.
  330. Burnham James L. ; Lawman Gary R., Methods to securely configure an FPGA using macro markers.
  331. New Bernard J. ; Harmon ; Jr. William J., Microprocessor with distributed registers accessible by programmable logic device.
  332. Gitlin Daniel ; Segers Dennis L. ; Hart Michael J., Mixed mode RAM/ROM cell using antifuses.
  333. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  334. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  335. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  336. Langhammer, Martin, Multi-operand floating point operations in a programmable integrated circuit device.
  337. Hart Michael J. ; Look Kevin T. ; Karpovich Yakov, Multilayer amorphous silicon antifuse.
  338. Langhammer, Martin, Multiple-precision processing block in a programmable integrated circuit device.
  339. Iwanczuk Roman ; Young Steven P. ; Schultz David P., Multiplexer array with shifted input traces.
  340. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y., Multiplier-accumulator circuitry and methods.
  341. Nance,Scott S.; Sheppard,Douglas P.; Sawyer,Nicholas J., Multiport RAM with programmable data port configuration.
  342. Sasaki,Paul T.; Menon,Suresh M.; Ghia,Atul V.; Cory,Warren E.; Verma,Hare K.; Freidin,Philip M., Network physical layer with embedded multi-standard CRC generator.
  343. Camarota Rafael C., Non-disruptive randomly addressable memory system.
  344. Dover,Lance W.; Rajguru,Chaitanya S.; Larsen,Robert E., Non-volatile configuration data storage for a configurable memory.
  345. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
  346. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
  347. Sample Stephen P. ; Butts Michael R., Optimized emulation and prototyping architecture.
  348. Sample, Stephen P.; Butts, Michael R., Optimized emulation and prototyping architecture.
  349. Alfke Peter H., Oscillator for measuring on-chip delays.
  350. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., PCI-compatible programmable logic devices.
  351. Cliff Richard G. ; Huang Joseph ; Sung Chiakang ; Wang Bonnie I., PCI-compatible programmable logic devices.
  352. Cliff, Richard G.; Heile, Francis B.; Huang, Joseph; Mendel, David W.; Pendersen, Bruce B.; Sung, Chiakang; Veenstra, Kerry; Wang, Bonnie I., PCI-compatible programmable logic devices.
  353. Cliff,Richard G; Heile,Francis B; Huang,Joseph; Mendel,David W; Pedersen,Bruce B; Sung,Chiakang; Veenstra,Kerry; Wang,Bonnie I, PCI-compatible programmable logic devices.
  354. Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.
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  356. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
  357. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
  358. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Christopher; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
  359. Trimberger Stephen M., PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays.
  360. Trimberger Stephen M., PLD having a window pane architecture with segmented interconnect wiring between logic block arrays.
  361. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
  362. New Bernard J. ; Erickson Charles R., Partially reconfigurable FPGA and method of operating same.
  363. Lee,Andy L; Chang,Wanli; McClintock,Cameron; Turner,John E; Johnson,Brian D; Hwang,Chiao Kai; Chang,Richard Y; Cliff,Richard G, Passage structures for use in low-voltage applications.
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  365. Lee, Andy L.; Chang, Wanli; McClintock, Cameron; Turner, John E.; Johnson, Brian D.; Hwang, Chiao Kai; Chang, Richard Yen-Hsiang; Cliff, Richard G., Passgate structures for use in low-voltage applications.
  366. Lee, Andy L; Chang, Wanli; McClintock, Cameron; Turner, John E; Johnson, Brian D; Hwang, Chiao Kai; Chang, Richard Yen Hsiang; Cliff, Richard G, Passgate structures for use in low-voltage applications.
  367. Chiakang Sung ; Robert R. N. Bielby ; Richard G. Cliff ; Edward Aung, Phase-locked loop circuitry for programmable logic devices.
  368. Sung Chiakang ; Bielby Robert R. N. ; Cliff Richard G. ; Aung Edward, Phase-locked loop circuitry for programmable logic devices.
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  372. Mauer, Volker; Langhammer, Martin, Pipelined systolic finite impulse response filter.
  373. Wu, Qinghong; Shen, Yinan; Liu, Liren, Placement processing for programmable logic devices.
  374. Langhammer, Martin, Polynomial calculations optimized for programmable integrated circuit device structures.
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  376. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
  377. Martin Vorbach DE; Robert Munch DE, Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like).
  378. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
  379. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
  380. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
  381. Mendel David Wolk (Sunnyvale CA), Product term based programmable logic array devices with reduced control memory requirements.
  382. Ong Randy T. ; Young Edel M., Programmable address decoder for programmable logic device.
  383. Gould Scott Whitney (South Burlington VT) Furtek Frederick Curtis (Menlo Park CA) Keyser ; III Frank Ray (Colchester VT) Worth Brian A. (Milton VT) Zittritsch Terrance John (Williston VT), Programmable array clock/reset resource.
  384. Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
  385. Langhammer, Martin, Programmable device using fixed and configurable logic to implement floating-point rounding.
  386. Langhammer, Martin, Programmable device using fixed and configurable logic to implement recursive trees.
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  388. Schultz,David P.; Douglass,Stephen M.; Young,Steven P.; Herron,Nigel G.; Vashi,Mehul R.; Sowards,Jane W., Programmable gate array and embedded circuitry initialization and processing.
  389. Douglass, Stephen M.; Young, Steven P.; Herron, Nigel G.; Vashi, Mehul R.; Sowards, Jane W., Programmable gate array having interconnecting logic to support embedded fixed logic circuitry.
  390. Syu, Tsung-Lu; Yee, Wilson Kaming, Programmable integrated circuit having built in test circuit.
  391. Ansari, Ahmad R., Programmable interactive verification agent.
  392. Yee, Wilson; Fox, Brian; Krishnamurthy, Sridhar; Reynolds, Bart; Winegarden, Steven, Programmable interface for a configurable system bus.
  393. Bertolet Allan Robert ; Clinton Kim P.N. ; Fuller Christine Marie ; Gould Scott Whitney ; Hartman Steven Paul ; Iadanza Joseph Andrew ; Keyser Frank Ray ; Millham Eric Ernest ; Reny Timothy Shawn ; W, Programmable inverter circuit used in a programmable logic cell.
  394. Leong William W. (San Francisco CA) Cliff Richard G. (Milpitas CA) McClintock Cameron (Mountain View CA), Programmable logic array device with grouped logic regions and three types of conductors.
  395. Francis B. Heile, Programmable logic array device with random access memory configurable as product terms.
  396. Heile Francis B., Programmable logic array device with random access memory configurable as product terms.
  397. Heile Francis B., Programmable logic array device with random access memory configurable as product terms.
  398. Heile, Francis B., Programmable logic array device with random access memory configurable as product terms.
  399. Mendel David W., Programmable logic array devices with enhanced interconnectivity between adjacent logic regions.
  400. Mendel David W., Programmable logic array devices with enhanced interconnectivity between adjacent logic regions.
  401. McClintock Cameron ; Leong William ; Cliff Richard G. ; Ahanin Bahram, Programmable logic array devices with interconnect lines of various lengths.
  402. McClintock Cameron ; Leong William ; Cliff Richard G. ; Ahanin Bahram, Programmable logic array devices with interconnect lines of various lengths.
  403. McClintock Cameron ; Leong William ; Cliff Richard G. ; Ahanin Bahram, Programmable logic array devices with interconnect lines of various lengths.
  404. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lane Christopher F. ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Ngo Ninh D. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ;, Programmable logic array integrated circuit architectures.
  405. Cliff Richard G. ; Heile Francis B. ; Sung Chiakang ; Wang Bonnie I. ; Pedersen Bruce B., Programmable logic array integrated circuit architectures.
  406. Richard G. Cliff ; Francis B. Heile ; Joseph Huang ; Christopher F. Lane ; Fung Fung Lee ; Cameron McClintock ; David W. Mendel ; Ninh D. Ngo ; Bruce B. Pedersen ; Srinivas T. Reddy ; Chiak, Programmable logic array integrated circuit architectures.
  407. Cliff Richard G. (Milpitas CA) Reddy Srinivas T. (Santa Clara CA) Raman Rina (Fremont CA) Cope L. Todd (San Jose CA) Huang Joseph (San Jose CA) Pedersen Bruce B. (San Jose CA), Programmable logic array integrated circuit devices.
  408. Cliff Richard G. ; Reddy Srinivas T. ; Jefferson David E. ; Raman Rina ; Cope L. Todd ; Lane Christopher F. ; Huang Joseph ; Heile Francis B. ; Pedersen Bruce B. ; Mendel David W. ; Lytle Craig S. ; , Programmable logic array integrated circuit devices.
  409. Cliff Richard G. ; Reddy Srinivas T. ; Raman Rina ; Cope L. Todd ; Huang Joseph ; Pedersen Bruce B., Programmable logic array integrated circuit devices.
  410. Cliff Richard G. ; Reddy Srinivas T. ; Raman Rina ; Cope L. Todd ; Huang Joseph ; Pedersen Bruce B., Programmable logic array integrated circuit devices.
  411. Cliff, Richard G.; Reddy, Srinivas T.; Jefferson, David Edward; Raman, Rina; Cope, L. Todd; Lane, Christopher F.; Huang, Joseph; Heile, Francis B.; Pedersen, Bruce B.; Mendel, David Wolk; Lytle, Crai, Programmable logic array integrated circuit devices.
  412. Richard G. Cliff ; Srinivas T. Reddy ; David Edward Jefferson ; Rina Raman ; L. Todd Cope ; Christopher F. Lane ; Joseph Huang ; Francis B. Heile ; Bruce B. Pedersen ; David Wolk Mendel ; C, Programmable logic array integrated circuit devices.
  413. Lee Fung F. (Milpitas CA) Tse John (El Cerrito CA), Programmable logic array integrated circuit devices with flexible carry chains.
  414. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lane Christopher F. ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Ngo Ninh D. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ;, Programmable logic array integrated circuit devices with interleaved logic array blocks.
  415. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., Programmable logic array integrated circuit devices with interleaved logic array blocks.
  416. Lytle Craig S. (Mountain View CA) Faria Donald F. (San Jose CA), Programmable logic array integrated circuit incorporating a first-in first-out memory.
  417. Craig S. Lytle ; Donald F. Faria, Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory.
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