[특허]Fault tolerant, synchronized twin computer system with error checking of I/O communication

Fault tolerant, synchronized twin computer system with error checking of I/O communication 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-011/16
출원번호	US-0382023 (1989-07-19)
발명자 / 주소	Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH) Mazur Dennis (Worcester MA) Munzer John (Brookline MA)
출원인 / 주소	Digital Equipment Corporation (Maynard MA 02)
인용정보	피인용 횟수 : 85 인용 특허 : 0

초록 ▼

A dual processor computer system includes a first processing system having a central processing unit which executes a series of data processing instructions, a data bus system for transferring data to and from the first central processing unit, a memory unit coupled to the first central processing unit, and a cross-link communications element for transferring data into and out of the first processing system. A similarly configured second processing system, operating independently of the first processing system, is also provided. The cross-link communications element associated with the second processing system is coupled to the cross-link communication element of the first processing system, for transferring data into the second processing system from the first processing system and for transferring data into the first processing system from the second computer system.

대표청구항 ▼

A dual processor computer system for connection to at least one input/output device comprising: a first processing system including a first central processing unit executing a series of data processing instructions including I/O instructions, a first dedicated bus coupled to said first central processing unit; a first memory unit coupled to said first central processing unit by said first dedicated bus, first communications means coupled to said first central processing unit for transferring data into and out of said first processing system; and a first data bus system coupled to said first communication means to transfer data to and from said first communication means; a second processing system, operating independently of said first processing system, said second processing system including a second central processing unit executing said series of data processing instructions including I/O instructions in the same order and approximately synchronously with said first central processing unit such that each of the instructions in said series of data processing instructions is executed approximately simultaneously by said first and second processing systems, a second dedicated bus coupled to said second central processing unit; a second memory unit coupled to said second central processing unit by said second dedicated bus, and second communications means, coupled to said second central processing unit and to said first communications means, for transferring data into and out of said second processing system; a second data bus system coupled to said second communications means for transferring data into and from said second communication means; and checking means, coupled to said first and second data bus systems, for comparing the data transferred out of said first and second processing systems by said first and second communications means, to said at least one input/output device during the approximately synchronous execution of said series of data processing instructions by said first and second processing systems in response to said I/O instructions to determine correct instruction execution by said first and second processing systems.

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연합인증

Fault tolerant, synchronized twin computer system with error checking of I/O communication 원문보기

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Fault tolerant, synchronized twin computer system with error checking of I/O communication 원문보기

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