초록 ▼

A BICMOS sense amplifier for content addressable memory circuits which combines the low power dissipation and high noise immunity of CMOS devices while maintaining the high drive capability and switching speed associated with bipolar devices. A combination of an RS latch at the output of a bipolar s

A BICMOS sense amplifier for content addressable memory circuits which combines the low power dissipation and high noise immunity of CMOS devices while maintaining the high drive capability and switching speed associated with bipolar devices. A combination of an RS latch at the output of a bipolar sense amplifier storing this output, and a clamping device at the base of the bipolar sensing amplifier shorting the base to ground, bring the bipolar device out of saturation after each sensing cycle to improve the switching speed. A biasing network is designed to bring the base of the bipolar sense amplifier up to a base-emitter turn-on voltage, while maintaining the output at a high level to improve voltage sensitivity and switching speed. Current mirrors are used in the biasing network to optimize performance over temperature and process variations.

대표청구항 ▼

A sense amplifier comprising: a bipolar transistor with a base for receipt of a sense signal, and a collector coupled to a current-source load; an RS latch with a input coupled to an input terminal for receipt of a RESET signal, a input coupled to said bipolar transistor collector, and an output cou

A sense amplifier comprising: a bipolar transistor with a base for receipt of a sense signal, and a collector coupled to a current-source load; an RS latch with a input coupled to an input terminal for receipt of a RESET signal, a input coupled to said bipolar transistor collector, and an output coupled to an output of said sense amplifier; and a clamping transistor with a first terminal coupled to said bipolar transistor base, a second terminal coupled to a ground terminal, and a third control terminal coupled to a complementary output of said latch.