초록 ▼

In accordance with the present invention, a memory system capable of indefinite sequential access to a contiguous address space without stutter is provided. The memory system has a memory array divided into left and right halves, column and row decoders, memory output register banks A and B, and con

In accordance with the present invention, a memory system capable of indefinite sequential access to a contiguous address space without stutter is provided. The memory system has a memory array divided into left and right halves, column and row decoders, memory output register banks A and B, and control logic. Upon initial access, the control logic determines whether, in the initial access data to be loaded in register banks A and B cross a row address boundary. If a row address boundary is crossed, data loaded into register bank A corresponds to data in one row in the right half of the memory array, and data in register bank B corresponds to data in the left half of the memory array in the next higher row. Thereafter, register banks A and B are interleaved for loading and output of memory data.

대표청구항 ▼

A memory system capable of providing output data upon receiving a two-part address comprising row and column addresses, said memory system comprising: a memory array having a plurality of memory cells organized into first and second portions of said memory array, each portion of said memory array ha

A memory system capable of providing output data upon receiving a two-part address comprising row and column addresses, said memory system comprising: a memory array having a plurality of memory cells organized into first and second portions of said memory array, each portion of said memory array having a plurality of word lines and a plurality of bit lines, wherein said row address selects one word line in each of said first and second portions of said memory array, wherein each column address selects a plurality of bit lines forming data words, and wherein word lines in said first portion of said memory array are activated independently from word lines in said second portion of said memory array; logic means for activating word lines and bit lines in said memory array such that a predetermined number of output data words corresponding to memory cells having contiguous addresses are provided from said memory array, wherein, when a subset of said number of output data words are stored in memory cells in said first portion of said memory array and the remaining of said number of output data words not in said subset are stored in memory cells of said second portion of said memory array, said logic means activates simultaneously in said first portion of said memory array a word line corresponding to said row address and in said second portion of said memory array a word line corresponding to said row address increased by one; and an internal register for receiving the data words corresponding to contents of memory cells accessed by said word lines in said first and second portions of said memory array, said internal register providing said data words as output data of said memory system one data word at a time in contiguous address order, said internal register providing each data word, after a first data word, at a time interval substantially less than the time interval between said memory system receiving said two-part address and said internal register providing said first data word, regardless of the position of said first data word in said internal register.