[특허]Dynamic random access memory

Dynamic random access memory 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G11C-007/00
출원번호	US-0813492 (1991-12-26)
우선권정보	JP-0418371 (1990-12-26)
발명자 / 주소	Okamura Junichi (Yokohama JPX) Furuyama Tohru (Tokyo JPX)
출원인 / 주소	Kabushiki Kaisha Toshiba (Kawasaki JPX 03)
인용정보	피인용 횟수 : 28 인용 특허 : 0

초록 ▼

A dynamic random access memory according to the present invention comprises a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.

대표청구항 ▼

A semiconductor memory device, comprising: dynamic memory cells arranged in a row and column array, each of said dynamic memory cells comprising a transfer MOS transistor of a first conductivity type and a capacitive element coupled to said transfer MOS transistor for storing data; word lines each connecting the dynamic memory cells in one row of said array; bit lines each connecting the dynamic memory cells in one column of said array; pads for receiving external address signals; address amplifying circuits coupled to said pads and responsive to the external address signals for generating first internal address signals for selecting a first number of said word lines in a normal operation mode; a control circuit responsive to a voltage stress test control signal for generating second internal address signals for selecting a second number of said word lines in a voltage stress test mode, the second number being greater than the first number; word line selecting circuits responsive to the first and second internal address signals for outputting word line selecting signals to select ones of said word lines; a word line driving voltage source for outputting a word line driving voltage; and word line driving circuits each coupled between corresponding ones of said word lines and said word line selecting circuits and responsive to said word line selecting signals for driving selected word lines, each of said word line driving circuits including: a first transistor of the first conductivity type having a first current terminal coupled to the corresponding one of said word line selecting circuits, a second current terminal, and a control terminal coupled to a power supply potential; a second transistor of a second conductivity type opposite the first conductivity type having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to the corresponding one of said word lines, and a control terminal coupled to said second current terminal of said first transistor; a third transistor of the first conductivity type having a first current terminal coupled to the corresponding ones of said word lines, a second current terminal coupled to a ground potential, and a control terminal coupled to the corresponding one of said word line selecting circuits; and a fourth transistor of the second conductivity type having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to said control terminal of said second transistor, and a control terminal coupled to the corresponding one of said word lines.

이 특허를 인용한 특허 (28)

Nishio Yoji (Hitachi JPX) Hirose Kosaku (Higashimurayama JPX) Hara Hideo (Akigawa JPX) Koike Katsunori (Hitachi JPX) Nemoto Kayoko (Hitachi JPX) Yamauchi Tatsumi (Hitachioota JPX) Murabayashi Fumio (, Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing sy.
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Nishio Yoji,JPX ; Hirose Kosaku,JPX ; Hara Hideo,JPX ; Koike Katsunori,JPX ; Nemoto Kayoko,JPX ; Yamauchi Tatsumi,JPX ; Murabayashi Fumio,JPX ; Yamada Hiromichi,JPX, Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them.
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Nishio, Yoji; Hirose, Kosaku; Hara, Hideo; Koike, Katsunori; Nemoto, Kayoko; Yamauchi, Tatsumi; Murabayashi, Fumio; Yamada, Hiromichi, Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them.
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Yoji Nishio JP; Kosaku Hirose JP; Hideo Hara JP; Katsunori Koike JP; Kayoko Nemoto JP; Tatsumi Yamauchi JP; Fumio Murabayashi JP; Hiromichi Yamada JP, Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them.
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Beffa Ray ; Waller William K., Method and apparatus for detecting intercell defects in a memory device.
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Ray Beffa ; William K. Waller, Method and apparatus for detecting intercell defects in a memory device.
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Michael A. Shore ; Patrick J. Mullarkey, Method and apparatus for multiple row activation in memory devices.
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Shore Michael A. ; Mullarkey Patrick J., Method and apparatus for multiple row activation in memory devices.
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Shore Michael A. ; Mullarkey Patrick J., Method and apparatus for multiple row activation in memory devices.
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Kirsch, Howard C., Method and system for accelerating coupling of digital signals.
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Kirsch, Howard C., Method and system for accelerating coupling of digital signals.
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Toda Haruki (Yokohama JPX), Multi-bank synchronous memory system with cascade-type memory cell structure.
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Toda Haruki (Yokohama JPX), Multi-bank synchronous memory system with cascade-type memory cell structure.
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Akaogi, Takao; Kasa, Yasushi, Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics.
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Akaogi, Takao; Takashina, Nobuaki; Kasa, Yasushi; Itano, Kiyoshi; Kawashima, Hiromi; Yamashita, Minoru, Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics.
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Akaogi, Takao; Takashina, Nobuaki; Kasa, Yasushi; Itano, Kiyoshi; Kawashima, Hiromi; Yamashita, Minoru; Kawamura, Shouichi, Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics.
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Kawashima Hiromi,JPX ; Kawamura Shouichi,JPX, Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics.
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Takao Akaogi JP, Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics.
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Takashina, Nobuaki; Kasa, Yasushi; Itano, Kiyoshi, Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics.
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McClure David C. (Carrollton TX), Periphery stress test for synchronous RAMs.
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Furuyama Tohru (Tokyo JPX), Semiconductor device and method of screening the same.
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Kaneko Tetsuya,JPX ; Ohsawa Takashi,JPX, Semiconductor integrated circuit including a boosted potential generating circuit.
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Kohno Fumihiro,JPX, Semiconductor memory device.
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Kohno Fumihiro,JPX, Semiconductor memory device.
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Kohno Fumihiro,JPX, Semiconductor memory device.
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Tsukasa Ooishi JP, Semiconductor memory device allowing acceleration testing, and a semi-finished product for an integrated semiconductor device that allows acceleration testing.
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Furutani, Kiyohiro; Asakura, Mikio; Katoh, Tetsuo, Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration.
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Kaneko Tetsuya (Kawasaki JPX) Ohsawa Takashi (Yokohama JPX), Semiconductor memory device including a boost potential generation circuit.
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