[특허]HEMT type semiconductor device having two semiconductor well layers

HEMT type semiconductor device having two semiconductor well layers 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-029/161 H01L-029/205 H01L-029/225
출원번호	US-0899699 (1992-06-17)
우선권정보	JP-0147741 (1991-06-20)
발명자 / 주소	Takikawa Masahiko (Kawasaki JPX)
출원인 / 주소	Fujitsu Limited (Kawasaki JPX 03)
인용정보	피인용 횟수 : 31 인용 특허 : 0

초록 ▼

A HEMT type semiconductor device includes a semiconductor substrate, a buffer semiconductor layer formed on the substrate, a first semiconductor well layer formed on the buffer layer and serving as a first conductivity type channel layer, a second semiconductor well layer formed on the first well layer and serving as a second conductivity type opposite the first conductivity, a channel layer and a potential barrier layer formed on the second well layer and forming a potential barrier for carriers. The substrate is made of GaAs or InP, and the layers are successively and epitaxially grown on the substrate. A two dimensional hole gas and a two dimensional electron gas are confined in the first well layer and in the second well layer, respectively.

대표청구항 ▼

A HEMT type semiconductor device comprising: a semiconductor substrate; a buffer semiconductor layer formed on said semiconductor substrate; a first semiconductor well layer formed on said buffer semiconductor layer and serving as a first conductivity type channel layer, which is selected from one of a p-channel layer and an n-channel layer; a second semiconductor well layer formed directly on said first semiconductor well layer and serving as a second conductivity type opposite said first conductivity type, channel layer and which is the other of said p-channel layer and said n-channel layer, one of said first and second semiconductor well layers being formed of a material having a higher valence band top energy level and a higher conduction band bottom energy level than a material forming the other of said first and second semiconductor well layers; and a potential barrier layer formed on said second semiconductor well layer and forming a potential barrier for carriers, said n-channel layer having a conduction band bottom energy level lower than a conduction band bottom energy level of said semiconductor substrate.

이 특허를 인용한 특허 (31)

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IPC	Description
A	생활필수품
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A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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연합인증

HEMT type semiconductor device having two semiconductor well layers 원문보기

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HEMT type semiconductor device having two semiconductor well layers 원문보기

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