[특허]Selectively configurable integrated circuit device for performing multiple digital signal processing functions

Selectively configurable integrated circuit device for performing multiple digital signal processing functions 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-007/52
출원번호	US-0946124 (1992-09-17)
발명자 / 주소	D\Luna Lionel J. (Rochester NY) Milch James R. (Pittsford NY) Kenney Timothy J. (Pittsford NY)
출원인 / 주소	Eastman Kodak Company (Rochester NY 02)
인용정보	피인용 횟수 : 43 인용 특허 : 0

초록 ▼

A single integrated circuit device is disclosed that is capable of selectively functioning in real time as either a sequential matrix multiplier, a parallel matrix multiplier, a convolver or a finite input response FIR filter in order to process image data. A core group of multipliers is used to provide the basic multiplication operation that is common to each of the desired image processing functions. Input data router unit, coefficient router units and an output data router unit are responsive to mode selection control signals, supplied to a mode selection port, to route the appropriate input data and coefficients to the core group of multipliers and to route the output of the adders to the correct output port(s) for each of the desired processing functions.

대표청구항 ▼

A selectively configurable integrated circuit device comprising: at least three data input ports, a coefficient input port, a mode selection input port, and three data output ports; an input data router unit coupled to the data input ports and the mode selection input port; at least three rows of multipliers, each row having a plurality of multipliers; at least three adder units corresponding to each row of multipliers, wherein inputs of each adder unit are coupled to the outputs of the multipliers within the multiplier row corresponding to each adder unit; an output data router unit coupled to the outputs of the adder units, the three data output ports, and the mode selection input port; and at least three coefficient routing units corresponding to the three rows of multipliers, wherein outputs of each coefficient routing unit are coupled to each multiplier within the corresponding multiplier row and to the adder unit coupled to the corresponding multiplier row; wherein the input data router transfers sequential data received from at least one of the data input ports into parallel data in response to a first operational mode control signal received from the mode selection port and supplies the parallel data to at least one row of multipliers, and wherein the input data router supplies data received from each data input port to all of the mulitplier rows in response to a second operational mode control signal received from the mode selection port.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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연합인증

Selectively configurable integrated circuit device for performing multiple digital signal processing functions 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

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연합인증

Selectively configurable integrated circuit device for performing multiple digital signal processing functions 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

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이 특허를 인용한 특허 (43)

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