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A semiconductor memory device having a plurality of memory cells disposed in the form of a matrix with column switch circuits and an address transition detecting circuit. The column switch circuits are each provided for each of said bit line pairs with their one end connected to a corresponding bit

A semiconductor memory device having a plurality of memory cells disposed in the form of a matrix with column switch circuits and an address transition detecting circuit. The column switch circuits are each provided for each of said bit line pairs with their one end connected to a corresponding bit line pair and their other end connected to a data line pair for changing the potential difference between the lines of the data line pair according to the potential difference between the lines of the corresponding bit line pair. Each switch circuit is selectively activated according to a column address decoder signal and an output pulse signal of the address transition detecting circuit.

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A semiconductor memory device comprising a plurality of memory cells disposed in the form of a matrix, a data line pair, a plurality of bit lie pairs each corresponding to a specific column, a plurality of word lines each corresponding to a specific row, a plurality of column switch circuits each pr

A semiconductor memory device comprising a plurality of memory cells disposed in the form of a matrix, a data line pair, a plurality of bit lie pairs each corresponding to a specific column, a plurality of word lines each corresponding to a specific row, a plurality of column switch circuits each provided for each of said bit line pairs with their one end connected to a corresponding bit lien pair and their other end connected to said data line pair for changing the potential difference between the lines of said data line pair according to the potential difference between the lines of said corresponding bit line pair, a plurality of precharger circuits for electrically charging said data line pair, an address transition detecting circuit for generating an output pulse signal in response to any change in a column address signal or a row address signal, and a column address decoder circuit for generating a selecting signal to select one of said column switch circuits in accordance with said column address signal, each memory cell being connected to one of said bit line paris and to one of said word lines, one of said word lines being selected in accordance with said row address signal, said column switch circuit selected by said selecting signal being activated when said output pulse signal is in an active state, so that said selected column switch circuit is both activated for a predetermined period and is disabled after said predetermined period at least when said row address signal changes.