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Method for interconnecting and system of interconnected processing elements by controlling network density 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/46
  • G06F-013/12
  • G06F-015/16
  • G06F-013/40
출원번호 US-0698866 (1991-05-13)
발명자 / 주소
  • Rolfe David B. (West Hurley NY)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 36  인용 특허 : 0

초록

Computer elements in a massively parallel computer system are interconnected in such a way that the number of connections per element can be balanced against the network diameter or worst case path length. This is done by creating a topology that maintains topological properties of hypercubes yet im

대표청구항

A computer system in a form of a non-binary hypercube comprising: a plurality of nodes, N, where N=bn, b and n being positive integers and b>2, each node having an identifying address numbered according to a number system base b; means for determining an address of each of said plurality of nodes; a

이 특허를 인용한 특허 (36)

  1. Passint, Randal S.; Thorson, Gregory M.; Stremcha, Timothy, Age-based network arbitration system and method.
  2. Faanes,Gregory J.; Scott,Steven L.; Lundberg,Eric P.; Moore, Jr.,William T.; Johnson,Timothy J., Decoupled scalar/vector computer architecture system and method.
  3. Georgiou,Christos John; Salapura,Valentina, Dynamic reallocation of data stored in buffers based on packet size.
  4. Galles Michael B. (Los Altos CA) Lenoski Daniel E. (San Jose CA), Hierarchical fat hypercube architecture for parallel processing systems.
  5. Passint Randal S. ; Thorson Greg ; Galles Michael B., Hybrid hypercube/torus architecture.
  6. Rolfe David B. ; Wack Andrew P., Incidence graph based communications and operations method and apparatus for parallel processing architecture.
  7. Rolfe David B. ; Wack Andrew P., Incidence graph based communications and operations method and apparatus for parallel processing architecture.
  8. Rolfe David B. ; Wack Andrew P., Incidence graph based communications and operations method and apparatus for parallel processing architecture.
  9. Kohn,James R., Indirectly addressed vector load-operate-store method and apparatus.
  10. Heller Steven K. ; Steele ; Jr. Guy L., Interconnection subsystem for interconnecting a predetermined number of nodes to form a Moebius strip topology.
  11. Heller Steven K. ; Steele ; Jr. Guy L., Interconnection subsystem for interconnecting a predetermined number of nodes to form an elongated brick-like non-square rectangular topology.
  12. Scott, Steven L., Latency tolerant distributed shared memory multiprocessor computer.
  13. Kessler Richard E. ; Oberlin Steven M. ; Scott Steven L., Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network an.
  14. Pautsch, Gregory W.; Pautsch, Adam, Method and apparatus for cooling electronic components.
  15. Kohn, James R., Method and apparatus for indirectly addressed vector load-add-store across multi-processors.
  16. Kohn,James R., Method and apparatus for indirectly addressed vector load-add-store across multi-processors.
  17. Kessler Richard E. ; Oberlin Steven M. ; Scott Steven L. ; Fromm Eric C., Method of handling arbitrary size message queues in which a message is written into an aligned block of external registers within a plurality of external registers.
  18. Birrittella Mark S. ; Kessler Richard E. ; Oberlin Steven M. ; Passint Randal S. ; Thorson Greg, Multiprocessor computer system with interleaved processing element nodes.
  19. Scott,Steven L.; Faanes,Gregory J.; Stephenson,Brick; Moore, Jr.,William T.; Kohn,James R., Multistream processing memory-and barrier-synchronization method and apparatus.
  20. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Rolfe David Bruce, N-dimensional modified hypercube.
  21. Kawaguchi,Shinichi, Network apparatus.
  22. Birrittella Mark S. ; Kessler Richard E. ; Oberlin Steven M. ; Passint Randal S. ; Thorson Greg, Networked multiprocessor system with global distributed memory and block transfer engine.
  23. Yoon Ki Song,KRX, Node disjoint path forming method for hypercube having damaged node.
  24. Heller Steven K. ; Steele ; Jr. Guy L., Non-hypercube interconnection subsystem having a subset of nodes interconnected using polygonal topology and other nod.
  25. Scott, Steven L.; Faanes, Gregory J.; Stephenson, Brick; Moore, Jr., William T.; Kohn, James R., Relaxed memory consistency model.
  26. Passint Randal S. ; Galles Michael B. ; Thorson Greg, Router table lookup mechanism.
  27. Klausler, Peter M., Scheduling synchronization of programs running as streams on multiple processors.
  28. Sheets,Kitrick; Williams,Josh; Gettler,Jonathan; Piatz,Steve; Hastings,Andrew B.; Hill,Peter; Bravatto,James G.; Kohn,James R.; Titus,Greg, Scheduling synchronization of programs running as streams on multiple processors.
  29. Thorson Greg ; Passint Randal S. ; Scott Steven L., Seralized race-free virtual barrier network.
  30. Kotler, Matthew J.; Gounares, Alexander G.; Fisher, Oliver G.; Morgan, Matthew D.; Franklin, Christopher Matthew, Spreadsheet fields in text.
  31. Scott Steven L. ; Kessler Richard E., System and method for fast barrier synchronization.
  32. Faanes, Gregory J.; Lundberg, Eric P.; Scott, Steven L.; Baird, Robert J., System and method for processing memory instructions using a forced order queue.
  33. Thorson Gregory M. (Altoona WI) Scott Steven L. (Eau Claire WI), System for randomly modifying virtual channel allocation and accepting the random modification based on the cost functio.
  34. Kessler Richard E. ; Oberlin Steven M. ; Scott Steven L. ; Fromm Eric C., Using external registers to extend memory reference capabilities of a microprocessor.
  35. Passint Randal S. ; Thorson Greg ; Galles Michael B., Virtual channel assignment in large torus systems.
  36. Thorson Gregory M., Virtual maintenance network in multiprocessing system having a non-flow controlled virtual maintenance channel.
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