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[미국특허] Integrated circuit polishing method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/302
출원번호 US-0858670 (1992-03-27)
발명자 / 주소
  • Yu Chris C. (Boise ID) Sandhu Gurtej S. (Boise ID) Doan Trung T. (Boise ID)
출원인 / 주소
  • Micron Technology, Inc. (Boise ID 02)
인용정보 피인용 횟수 : 147  인용 특허 : 0

초록 ▼

A semiconductor wafer has a surface layer to be planarized in a chemical mechanical polishing (CMP) process. An area of the layer that is higher than another area is altered so that the removal rate is higher. For example, if the surface layer is TEOS oxide, the higher layer may be bombarded with bo

대표청구항 ▼

A method of fabrication of an integrated circuit, said method comprising the steps of: providing a semiconductor wafer having a surface layer of a material to be planarized in a chemical mechanical polishing process; masking said surface layer to define first and second laterally adjacent portions o

이 특허를 인용한 특허 (147) 인용/피인용 타임라인 분석

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