이 특허를 인용한 특허 (87)

1. Cardone, Frank; Chu, Jack Oon; Ismail, Khalid EzzEldin, Abrupt delta-like doping in Si and SiGe films by UHV-CVD.

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2. Boles Timothy Edward, Ballasting of high power silicon-germanium heterojunction biploar transistors.

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3. Enicks, Darwin Gene; Carver, Damian, Bandgap and recombination engineered emitter layers for SiGe HBT performance optimization.

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4. Enicks,Darwin Gene; Carver,Damian, Bandgap engineered mono-crystalline silicon cap layers for SiGe HBT performance enhancement.

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5. Fitzgerald, Eugene A., Buried channel strained silicon FET using a supply layer created through ion implantation.

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6. Fitzgerald, Eugene A., Buried channel strained silicon FET using a supply layer created through ion implantation.

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7. Fitzgerald, Eugene A., Buried channel strained silicon FET using a supply layer created through ion implantation.

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8. Currie,Matthew T., Control of strain in device layers by prevention of relaxation.

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9. Currie,Matthew T., Control of strain in device layers by selective relaxation.

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10. Fitzgerald, Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.

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11. Fitzgerald,Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.

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12. Fitzgerald,Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.

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13. Lochtefeld, Anthony J.; Langdo, Thomas A.; Westhoff, Richard, Elevated source and drain elements for strained-channel heterojuntion field-effect transistors.

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14. Ye, Zhiyuan; Li, Xuebin; Chopra, Saurabh; Kim, Yihwan, Epitaxy of high tensile silicon alloy for tensile strain applications.

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15. Ye, Zhiyuan; Li, Xuebin; Chopra, Saurabh; Kim, Yihwan, Epitaxy of high tensile silicon alloy for tensile strain applications.

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16. Wu,Kenneth C.; Fitzgerald,Eugene A.; Taraschi,Gianni; Borenstein,Jeffrey T., Etch stop layer system.

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17. Asenov, Asen, Fluctuation resistant FDSOI transistor with implanted subchannel.

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18. Asenov, Asen, Fluctuation resistant low access resistance fully depleted SOI transistor with improved channel thickness control and reduced access resistance.

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19. Asenov, Asen, Gate recessed FDSOI transistor with sandwich of active and etch control layers.

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20. Zhong, Fan; Bornstein, Jonathan G., GePSG core for a planar lightwave circuit.

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21. Fitzgerald, Eugene A., Heterointegration of materials using deposition and bonding.

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22. Adam, Thomas N.; Harame, David L.; Liu, Qizhi; Reznicek, Alexander, Heterojunction bipolar transistor with epitaxial emitter stack to improve vertical scaling.

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23. Currie, Matthew T., Hybrid fin field-effect transistor structures and related methods.

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24. Fitzgerald, Eugene A., Low threading dislocation density relaxed mismatched epilayers without high temperature growth.

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25. Asenov, Asen; Roy, Gareth, Manufacture of a variation resistant metal-oxide-semiconductor field effect transistor (MOSFET).

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26. Meyerson Bernard Steele, Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers.

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27. Enicks,Darwin Gene, Method and system for controlled oxygen incorporation in compound semiconductor films for device performance enhancement.

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28. Silver,Eric H.; Madden,Norman W.; Robinson,McDonald; Lawrence,Lamonte H., Method for making an epitaxial germanium temperature sensor.

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29. Shenai Khatkhate,Deodatta Vinayak; Power,Michael Brendan, Method of depositing a metal-containing film.

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30. Woelk,Egbert; Shenai Khatkhate,Deodatta Vinayak, Method of depositing germanium-containing films.

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31. Fitzgerald, Eugene A.; Gerrish, Nicole, Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs.

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32. Fitzgerald, Eugene A.; Gerrish, Nicole, Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS.

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33. Cheng,Zhiyuan; Fitzgerald,Eugene A.; Antoniadis,Dimitri A., Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers.

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34. Boles Timothy Edward, Method of fabricating polysilicon based resistors in Si-Ge heterojunction devices.

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35. Fu,Li; Panayil,Sheeba J.; Wang,Shulin; Quentin,Christopher G.; Luo,Lee; Chen,Aihua; Tao,Xianzhi, Method of forming a controlled and uniform lightly phosphorous doped silicon film.

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36. Fu,Li; Panayil,Sheeba J.; Wang,Shulin; Quentin,Christopher G.; Luo,Lee; Chen,Aihua; Tao,Xianzhi, Method of forming a controlled and uniform lightly phosphorous doped silicon film.

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37. Huisman Frederikus R. J.,NLX ; De Boer Wiebe B.,NLX ; Bulik Oscar J. A.,NLX ; Dekker Ronald,NLX, Method of manufacturing a semiconductor device with a pn junction provided through epitaxy.

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38. Asenov, Asen; Roy, Gareth, Method of manufacturing variation resistant metal-oxide-semiconductor field effect transistor (MOSFET).

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39. Dube, Abhishek; Li, Xuebin; Huang, Yi-Chiau; Chung, Hua; Chu, Schubert S., Method to enhance growth rate for selective epitaxial growth.

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40. Dube, Abhishek; Li, Xuebin; Huang, Yi-Chiau; Chung, Hua; Chu, Schubert S., Method to enhance growth rate for selective epitaxial growth.

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41. Tomasini,Pierre; Cody,Nyles; Arena,Chantal, Method to planarize and reduce defect density of silicon germanium.

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42. Fitzgerald,Eugene; Currie,Matthew, Methods for fabricating strained layers on semiconductor substrates.

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43. Fitzgerald,Eugene; Currie,Matthew, Methods for fabricating strained layers on semiconductor substrates.

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44. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming III-V semiconductor device structures.

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45. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain.

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46. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes.

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47. Fitzgerald, Eugene A., Methods of fabricating contact regions for FET incorporating SiGe.

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48. Vineis,Christopher; Yang,Vicky; Currie,Matthew; Westhoff,Richard; Leitz,Christopher, Methods of fabricating semiconductor heterostructures.

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49. Langdo,Thomas A.; Lochtefeld,Anthony J., Methods of fabricating semiconductor structures having epitaxially grown source and drain elements.

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50. Langdo,Thomas A.; Lochtefeld,Anthony J., Methods of fabricating semiconductor structures having epitaxially grown source and drain elements.

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51. Currie,Matthew T., Methods of forming hybrid fin field-effect transistor structures.

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52. Currie,Matthew T.; Hammond,Richard, Methods of forming reacted conductive gate electrodes.

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53. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods of forming strained-semiconductor-on-insulator device structures.

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54. Lochtefeld,Anthony J.; Langdo,Thomas A.; Hammond,Richard; Currie,Matthew T.; Braithwaite,Glyn; Fitzgerald,Eugene A., Methods of forming strained-semiconductor-on-insulator finFET device structures.

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55. Shenai-Khatkhate, Deodatta Vinayak; Power, Michael Brendan, Organometallic compounds.

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56. Adam, Thomas N.; Harame, David L.; Liu, Qizhi; Reznicek, Alexander, Power sige heterojunction bipolar transistor (HBT) with improved drive current by strain compensation.

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57. Shenai Khatkhate,Deodatta Vinayak, Preparation of group IVA and group VIA compounds.

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58. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Process for producing semiconductor article using graded epitaxial growth.

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59. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Process for producing semiconductor article using graded epitaxial growth.

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60. Braithwaite, Glyn; Hammond, Richard; Currie, Matthew, RF circuits including transistors having strained material layers.

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61. Braithwaite, Glyn; Hammond, Richard; Currie, Matthew, RF circuits including transistors having strained material layers.

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62. Currie, Matthew T.; Hammond, Richard, Reacted conductive gate electrodes.

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63. Vineis, Christopher J.; Westhoff, Richard; Bulsara, Mayank, Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy.

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64. Fitzgerald,Eugene A., Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits.

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65. Fitzgerald,Eugene A., Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits.

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66. Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.

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67. Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.

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68. Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.

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69. Cheng, Zhiyuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A., Semiconductor device structure.

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70. Vineis,Christopher; Yang,Vicky; Currie,Matthew; Westhoff,Richard; Leitz,Christopher, Semiconductor heterostructures and related methods.

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71. Westhoff,Richard; Yang,Vicky; Currie,Matthew; Vineis,Christopher; Leitz,Christopher, Semiconductor heterostructures having reduced dislocation pile-ups.

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72. Westhoff, Richard; Yang, Vicky K.; Currie, Matthew T.; Vineis, Christopher; Leitz, Christopher, Semiconductor heterostructures having reduced dislocation pile-ups and related methods.

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73. Cardone,Frank; Chu,Jack Oon; Ismail,Khalid EzzEldin, Semiconductor structure having an abrupt doping profile.

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74. Currie, Matthew T.; Lochtefeld, Anthony J.; Hammond, Richard; Fitzgerald, Eugene A., Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.

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75. Currie, Matthew T.; Lochtefeld, Anthony J.; Hammond, Richard; Fitzgerald, Eugene A., Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.

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76. Currie, Matthew; Lochtefeld, Anthony; Hammond, Richard; Fitzgerald, Eugene, Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.

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77. Westhoff,Richard; Vineis,Christopher J.; Currie,Matthew T.; Yang,Vicky T.; Leitz,Christopher W., Semiconductor structures with structural homogeneity.

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78. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Semiconductor substrate structure.

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79. Currie,Matthew T.; Lochtefeld,Anthony J., Shallow trench isolation process.

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80. Arena,Chantal J.; Tomasini,Pierre; Cody,Nyles W., SiGe rectification process.

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81. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained germanium-on-insulator device structures.

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82. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.

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83. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.

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84. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures with elevated source/drain regions.

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85. Langdo,Thomas A.; Currie,Matthew T.; Braithwaite,Glyn; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator finFET device structures.

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86. Kapoor, Ashok K.; Asenov, Asen, Variation resistant MOSFETs with superior epitaxial properties.

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87. Asenov, Asen; Roy, Gareth, Variation resistant metal-oxide-semiconductor field effect transistor (MOSFET).

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