IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
|
| 국제특허분류(IPC7판) |
|
| 출원번호 |
US-0752166
(1991-08-22)
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| 우선권정보 |
EP-0201501 (1988-07-13) |
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발명자
/ 주소 |
- Dekker Robertus W. C. (Eindhoven NLX) Thijssen Aloysius P. (Pijnacker NLX) Beenker Franciscus P. M. (Eindhoven NLX) Jansen Joris F. P. (Eindhoven NLX)
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| 출원인 / 주소 |
- U.S. Philips Corporation (New York NY 02)
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| 인용정보 |
피인용 횟수 :
69 인용 특허 :
0 |
초록
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A memory device that contains a static RAM memory is provided with data input and data output registers, an address register, and a control register for storing various control signals. The RAM has three principal modes: a. in a normal mode, all registers are accessible externally so that the memory
A memory device that contains a static RAM memory is provided with data input and data output registers, an address register, and a control register for storing various control signals. The RAM has three principal modes: a. in a normal mode, all registers are accessible externally so that the memory may fulfill its standard function, b. in a scan-state, all the cited register constitute a synchronous shift register that may be serially written with a test pattern and serially read with a result pattern; in this way the memory may be subjected to a test according to the scan test principle, c. in a self test state the communication with the outer world is shut off, the address register counts through successive addresses, the memory is cycled through read-modify or read-modify-read operations, and the data read is conversed to a signature pattern for subsequent scan-out. In this way a quasi stand-alone test facility is realized. Various additional features may be implemented.
대표청구항
▼
A memory device comprising: a) a static RAM-memory; b) an address register, a data input register, a data output register, and a control register all operatively coupled to the RAM for executing accesses to said memory, c) said address, data input and control registers having externally accessible f
A memory device comprising: a) a static RAM-memory; b) an address register, a data input register, a data output register, and a control register all operatively coupled to the RAM for executing accesses to said memory, c) said address, data input and control registers having externally accessible functional interconnections for information communication, d) all said registers comprising respective parts of a serially activatable test scan chain means, and e) first control means for activating said memory device alternatively in a scan-state, an operational state, and an independent self-test state, wherein: in a said scan-state, said test scan chain mean is operative as at least one serial shift register; in said operational state, at least said address register, said data input register, and said control register are operatively coupled to the memory; and in said self-test state, during a time when there is an absence of any information communication via any information input of the memory device, said address register, said data input register and said control register are operatively coupled to the memory for autonomously generating successive data test patterns and address test patterns during a plurality of distinct cycles through RAM, and for switching between reading and writing; and said data output register is operative for receiving successive data result patterns and includes conversion means for converting successive data result patterns to a signature pattern; said address register and data input register being provided with sequencing means for converting an initialization pattern sequentially to a succession of sequel patterns, and wherein said conversion means are operative in synchronism with the generation of said sequel patterns, said data input register being provided with a preset mechanism for in the latter register producing a partial test pattern that has a maximum number of 1-0 changeovers between successive bit positions, and said sequencing means has second control means for from said partial test pattern generating successive further partial test patterns in a partial sequence, wherein in said sequence each 1-0 changeover between a random pair of bit positions thereof occurs at least once.
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