이 특허를 인용한 특허 (212)

1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.

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7. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.

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8. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.

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9. Wright Adam, Apparatus and method for generating configuration and test files for programmable logic devices.

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10. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.

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14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.

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15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.

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16. Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.

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17. Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.

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18. Ting,Benjamin S., Architecture and interconnect scheme for programmable logic circuits.

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19. Hogenauer, Eugene B., Arithmetic node including general digital signal processing functions for an adaptive computing machine.

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20. Howard, Ric; Katragadda, Ramana V., Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture.

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21. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.

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22. Vorbach, Martin, Chip including memory element storing higher level memory data on a page by page basis.

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23. Kao,Sean; Rahman,Arifur; Anderson,James, Circuit for and method of enabling partial reconfiguration of a device having programmable logic.

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24. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.

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25. Edwards, Eric E., Circuit having a programmable circuit and method of validating a bitstream loaded into a programmable device.

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26. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.

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27. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.

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28. Kazunori Ohuchi JP; Masako Yoshida JP; Yukihito Oowaki JP; Hiroshige Fujii JP; Masatoshi Sekine JP, Configurable integrated circuit and method of testing the same.

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29. Vorbach, Martin; Nuckel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.

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30. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.

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31. Couts-Martin Chris ; Herrmann Alan, Configuration memory integrated circuit.

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32. Couts-Martin Chris ; Herrmann Alan, Configuration memory integrated circuit.

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33. Couts-Martin, Chris; Herrmann, Alan, Configuration memory integrated circuit.

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34. Mirsky,Ethan; French,Robert; Eslick,Ian, Controlling multiple context processing elements based on transmitted message containing configuration data, address mask, and destination indentification.

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35. Hamano, Hiroshi; Yamamoto, Takuji; Kuroyanagi, Satoshi, Crosspoint switch circuit and switch cell electronic circuit.

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36. Rotem Eran,ILX ; Yoeli Uzi,ILX ; Phillips Richard Stephen,CAX, Customizable integrated circuit device.

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37. DeHon Andre ; Bolotski Michael ; Knight ; Jr. Thomas F., DPGA-coupled microprocessors.

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38. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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39. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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40. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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41. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.

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42. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.

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43. Vorbach, Martin, Data processing system.

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44. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing system having integrated pipelined array data processor.

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45. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.

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46. Fink Hans-Joerg,DEX, Device for setting operating parameters in a plurality of programmable integrated circuits.

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47. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.

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48. Vorbach Martin Andreas,DEX ; Munch Robert Markus,DEX, Dynamically reconfigurable data processing system.

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49. Beal Samuel W. ; Kaptonoglu Sinan ; Lien Jung-Cheun ; Shu William ; Chan King W. ; Plants William C., Enhanced field programmable gate array.

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50. Furtek, Frederick Curtis; Master, Paul L., External memory controller.

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51. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.

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52. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.

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53. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.

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54. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.

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55. Alfke Peter H., FPGA control structure for self-reconfiguration.

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56. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA logic cell internal structure including pair of look-up tables.

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57. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector clock lines.

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58. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector reset lines.

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59. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells.

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60. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array with distributed RAM and increased cell utilization.

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61. John E. McGowan, Field programmable gate array with mask programmed input and output buffers.

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62. McGowan John E., Field programmable gate array with mask programmed input and output buffers.

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63. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.

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64. Martin Vorbach DE; Robert Munch DE, I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures.

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65. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.

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66. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.

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67. Vorbach,Martin; M��nch,Robert, I/O and memory bus system for DFPS and units with two-or multi-dimensional programmable cell architectures.

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68. Vorbach Martin,DEX ; Munch Robert,DEX, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.

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69. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.

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70. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.

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71. Vorbach,Martin; M？nch,Robert, I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures.

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72. Furtek, Frederick Curtis; Master, Paul L.; Plunkett, Robert Thomas, Input/output controller node in an adaptable computing environment.

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73. Andre DeHon ; Ethan Mirsky ; Thomas F. Knight, Jr., Intermediate-grain reconfigurable processing device.

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74. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.

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75. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.

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76. DeHon, Andre; Mirsky, Ethan; Knight, Jr., Thomas F., Intermediate-grain reconfigurable processing device.

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77. Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.

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78. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.

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79. Heidari-Bateni, Ghobad; Sambhwani, Sharad D., Internal synchronization control for adaptive integrated circuitry.

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80. Mirsky, Ethan; French, Robert; Eslick, Ian, Local control of multiple context processing elements with configuration contexts.

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81. Mirsky, Ethan; French, Robert; Eslick, Ian, Local control of multiple context processing elements with major contexts and minor contexts.

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82. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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83. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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84. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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85. Francis B. Heile, Logic device architecture and method of operation.

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86. Heile Francis B., Logic device architecture and method of operation.

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87. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.

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88. Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.

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89. Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.

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90. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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91. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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92. John Nathan, Memory device having a switchable clock output and method therefor.

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93. Mirsky Ethan A., Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements.

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94. Mirsky, Ethan A., Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements.

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95. Mirsky,Ethan A., Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements.

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96. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple cont.

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97. Ethan Mirsky ; Robert French ; Ian Eslick, Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements.

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98. Edwards, Eric E.; Shimanek, Schuyler E.; Young, Philip A.; Reilly, Steven T.; Wennekamp, Wayne E., Method and apparatus for data transfer validation.

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99. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for position independent reconfiguration in a network of multiple context processing elements.

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100. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for retiming in a network of multiple context processing elements.

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101. Mirsky, Ethan; French, Robert; Eslick, Ian, Method and apparatus for retiming in a network of multiple context processing elements.

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102. Mirsky,Ethan; French,Robert; Eslick,Ian, Method and apparatus for retiming in a network of multiple context processing elements.

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103. Pani, Peter M.; Ting, Benjamin S., Method and apparatus for universal program controlled bus architecture.

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104. Pani,Peter M.; Ting,Benjamin S., Method and apparatus for universal program controlled bus architecture.

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105. Nadeau-Dostie, Benoit; Cote, Jean-Francois, Method and circuitry for controlling clocks of embedded blocks during logic bist test mode.

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106. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.

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107. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.

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108. Master, Paul L., Method and system for achieving individualized protected space in an operating system.

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109. Master, Paul L., Method and system for creating and programming an adaptive computing engine.

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110. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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111. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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112. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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113. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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114. Craft David John ; Gould Scott Whitney ; Keyser ; III Frank Ray ; Worth Brian, Method and system for programming a gate array using a compressed configuration bit stream.

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115. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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116. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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117. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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118. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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119. Master, Paul L.; Scheuermann, W. James, Method and system for reducing the time-to-market concerns for embedded system design.

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120. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).

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121. Vorbach, Martin, Method for debugging reconfigurable architectures.

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122. Vorbach, Martin, Method for debugging reconfigurable architectures.

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123. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.

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124. Vorbach,Martin, Method for debugging reconfigurable architectures.

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125. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.

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126. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.

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127. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.

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128. Vorbach, Martin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.

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129. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.

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130. Vorbach Martin,DEX ; Munch Robert,DEX, Method for the automatic address generation of modules within clusters comprised of a plurality of these modules.

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131. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.

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132. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.

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133. Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).

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134. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).

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135. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Method of processing data with an array of data processors according to application ID.

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136. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.

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137. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.

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138. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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139. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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140. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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141. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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142. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.

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143. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.

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144. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable unit.

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145. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.

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146. Trimberger,Stephen M., Methods and circuits for preventing the overwriting of memory frames in programmable logic devices.

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147. Trimberger,Stephen M., Methods and circuits for protecting proprietary configuration data for programmable logic devices.

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148. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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149. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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150. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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151. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.

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152. Vorbach, Martin, Methods and devices for treating and/or processing data.

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153. Mirsky,Ethan; French,Robert; Eslick,Ian, Multi-channel bi-directional bus network with direction sideband bit for multiple context processing elements.

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154. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Multi-processor bus and cache interconnection system.

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155. Vorbach, Martin, Multi-processor with selectively interconnected memory units.

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156. Vorbach, Martin, Multiprocessor having associated RAM units.

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157. Vorbach, Martin; Baumgarte, Volker, Multiprocessor having runtime adjustable clock and clock dependent power supply.

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158. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.

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159. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.

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160. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.

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161. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.

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162. Vorbach Martin,DEX ; Munch Robert,DEX, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like).

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163. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).

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164. Martin Vorbach DE; Robert Munch DE, Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like).

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165. Scheuermann,W. James, Processing architecture for a reconfigurable arithmetic node.

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166. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.

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167. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.

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168. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.

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169. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.

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170. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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171. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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172. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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173. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.

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174. Tony K. Ngai ; Rakesh H. Patel ; Srinivas T. Reddy ; Richard G. Cliff, Programmable logic device having embedded dual-port random access memory configurable as single-port memory.

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175. Trimberger,Stephen M., Programmable logic device that supports secure and non-secure modes of decryption-key access.

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176. Craig S. Lytle ; Kerry S. Veenstra, Programmable logic device with highly routable interconnect.

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177. Lytle Craig S. ; Veenstra Kerry S., Programmable logic device with highly routable interconnect.

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178. Lytle Craig S. ; Veenstra Kerry S. ; Heile Francis B., Programmable logic device with highly routable interconnect.

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179. Shieh Jhy-Jer ; Tang Dandas Kenneth, Programmable output buffer and method for programming.

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180. Kobayashi Naohiro,JPX, Programmable semiconductor device providing security of circuit information.

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181. Vorbach, Martin, Reconfigurable elements.

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182. Vorbach, Martin, Reconfigurable elements.

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183. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.

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184. John Morelli ; H. Richard Kendall, Reconfigurable logic for a computer.

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185. Vorbach,Martin; M？nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.

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186. Vorbach, Martin, Reconfigurable sequencer structure.

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187. Vorbach, Martin, Reconfigurable sequencer structure.

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188. Vorbach, Martin, Reconfigurable sequencer structure.

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189. Vorbach, Martin, Reconfigurable sequencer structure.

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190. Vorbach,Martin, Reconfigurable sequencer structure.

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191. Trimberger Stephen M., Reprogrammable instruction set accelerator.

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192. Trimberger Stephen M., Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page tab.

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193. Vorbach, Martin; Bretz, Daniel, Router.

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194. Vorbach,Martin; Bretz,Daniel, Router.

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195. Vorbach Martin,DEX ; Munch Robert,DEX, Run-time reconfiguration method for programmable units.

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196. Vorbach,Martin; M？nch,Robert, Run-time reconfiguration method for programmable units.

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197. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.

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198. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.

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199. Apland James M. ; Eaton David D. ; Chan Andrew K., Security antifuse that prevents readout of some but not other information from a programmed field programmable gate arr.

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200. Trimberger,Stephen M., Self-erasing memory for protecting decryption keys and proprietary configuration data.

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201. Master,Paul L.; Watson,John, Storage and delivery of device features.

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202. Ahmed, Sebastian, System and method to control one time programmable memory.

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203. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.

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204. Ip Tony K., System for generating chip select signals based on coded and uncoded address signals.

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205. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.

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206. Bocchino Vincent T., Technique for preconditioning I/Os during reconfiguration.

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207. Bocchino Vincent T., Technique for preconditioning I/Os during reconfiguration.

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208. Mirsky, Ethan; French, Robert; Eslick, Ian, Three level direct communication connections between neighboring multiple context processing elements.

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209. Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.

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210. Pedersen,Bruce B, Versatile RAM for a programmable logic device.

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211. Pedersen,Bruce B, Versatile RAM for programmable logic device.

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212. DeRoo David T. ; Nicol Mark D. ; Krau Michael P., Write once read only registers.

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