이 특허를 인용한 특허 (29)

1. Horch, Andrew; Robins, Scott, Fin thyristor-based semiconductor device.

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2. Horch,Andrew; Robins,Scott, Fin thyristor-based semiconductor device.

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3. Wang,Hongmei; Zahurak,John K., Fully-depleted (FD) (SOI) MOSFET access transistor.

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4. Wang,Hongmei; Zahurak,John K., Fully-depleted (FD) (SOI) MOSFET access transistor.

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5. Wang, Hongmei; Zahurak, John K., Fully-depleted (FD) (SOI) MOSFET access transistor and method of fabrication.

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6. Wang, Hongmei; Zahurak, John K., Fully-depleted (FD)(SOI) MOSFET access transistor and method of fabrication.

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7. Li, You; Gauthier, Jr., Robert J.; Mitra, Souvick; Yu, Mickey, Low capacitance electrostatic discharge (ESD) devices.

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8. Mollison, Karl W.; LeCaptain, Angela M.; Burke, Sandra E.; Cromack, Keith R.; Tarcha, Peter J.; Chen, Yen-Chih J.; Toner, John L., Medical devices containing rapamycin analogs.

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9. Horch, Andrew, Method for making an inlayed thyristor-based device.

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10. Wang,Hongmei; Zahurak,John K., Method of forming fully-depleted (FD) SOI MOSFET access transistor.

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11. Tiwari Sandip ; Wind Samuel Jonas, Method of making self-aligned dual gate MOSFET with an ultranarrow channel.

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12. Pradeep, Yelehanka; Zheng, Jia Zhen; Chan, Lap; Quek, Elgin; Sundaresan, Ravi; Pan, Yang; Meng, James Lee Yong; Keung, Ying, Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel.

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13. Fernando Gonzalez ; Er-Xuan Ping, Methods of forming DRAM assemblies, transistor devices, and openings in substrates.

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14. Gonzalez, Fernando; Ping, Er-Xuan, Methods of forming DRAM assemblies, transistor devices, and openings in substrates.

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15. Schuele,Paul J.; Voutsas,Apostolos T., Multi-planar layout vertical thin-film transistor inverter.

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16. Braithwaite, Glyn; Hammond, Richard; Currie, Matthew, RF circuits including transistors having strained material layers.

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17. Kirk Prall, SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, MEMORY CIRCUITRY EMPLOYING SEMICONDUCTOR-ON-INSULATOR TRANSISTORS, METHOD OF FORMING A SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, AND METHOD OF FORMING MEMORY CIRCU.

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18. Prall, Kirk, SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, MEMORY CIRCUITRY EMPLOYING SEMICONDUCTOR-ON-INSULATOR TRANSISTORS, METHOD OF FORMING A SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, AND METHOD OF FORMING MEMORY CIRCU.

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19. Currie, Matthew T.; Lochtefeld, Anthony J.; Hammond, Richard; Fitzgerald, Eugene A., Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.

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20. Currie, Matthew T.; Lochtefeld, Anthony J.; Hammond, Richard; Fitzgerald, Eugene A., Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.

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21. Currie, Matthew; Lochtefeld, Anthony; Hammond, Richard; Fitzgerald, Eugene, Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.

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22. Currie, Matthew; Lochtefeld, Anthony; Hammond, Richard; Fitzgerald, Eugene, Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.

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23. Kirk Prall, Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors.

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24. Einav, Moshe, Thin film field effect transistor.

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25. Wu, Chen-Yi; Kao, Yih-Chyun; Huang, Chun-Yao, Thin film transistor and pixel structure having the thin film transistor.

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26. Boles Timothy ; O'Keefe Matthew F. ; Sledziewski John M., Ultrahigh vacuum deposition of silicon (Si-Ge) on HMIC substrates.

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27. Emmi Peter A. ; Park Byeongju, Vertical channel field effect transistor.

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28. Chu Jack Oon (Astoria NY) Hsu Louis Lu-Chen (Fishkill NY) Mandelman Jack Allan (Stormville NY) Sun Yuan-Chen (Katonah NY) Taur Yuan (Bedford NY), Vertical double-gate field effect transistor.

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29. Chu Jack Oon ; Hsu Louis Lu-Chen ; Mandelman Jack Allan ; Sun Yuan-Chen ; Taur Yuan, Vertical double-gate field effect transistor.

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